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[/] [robust_reg/] [trunk/] [src/] [base/] [regfile.v] - Diff between revs 14 and 16

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/////////////////////////////////////////////////////////////////////
<##//////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////          eyal@provartec.com                                 ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
////  Downloaded from: http://www.opencores.org                  ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////##>
 
 
OUTFILE REGNAME_regfile.v
OUTFILE PREFIX_regfile.v
INCLUDE def_regfile.txt
INCLUDE def_regfile.txt
 
 
ITER RX GROUP_REGS.NUM
ITER RX GROUP_REGS.NUM
 
 
module REGNAME_regfile (PORTS);
module PREFIX_regfile (PORTS);
 
 
   parameter            ADDR_BITS = 16;
   parameter            ADDR_BITS = 16;
 
 
   input                clk;
   input                clk;
   input                reset;
   input                reset;
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           begin
           begin
             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD GROUP_REGRX.WIDTH'dGROUP_REGRX.DEFAULT;     //GROUP_REGRX.DESC
             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD GROUP_REGRX.WIDTH'dGROUP_REGRX.DEFAULT;     //GROUP_REGRX.DESC
           end
           end
     else if (wr_regRX)
     else if (wr_regRX)
           begin
           begin
             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD pwdata[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START];
             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD pwdata[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.FIRST_BIT-1):GROUP_REGRX.FIRST_BIT];
           end
           end
 
 
   ENDIF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW)
   ENDIF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW)
        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_WO) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_WO) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_IW) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_IW) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
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        //---------------------- Read Operations ----------------------------
        //---------------------- Read Operations ----------------------------
     always @(*)
     always @(*)
     begin
     begin
           rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX  = {32{1'b0}};
           rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX  = {32{1'b0}};
 
 
           rd_regRX[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START] = GROUP_REGRX.SON(TYPE != TYPE_WO);     //GROUP_REGRX.DESC
           rd_regRX[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.FIRST_BIT-1):GROUP_REGRX.FIRST_BIT] = GROUP_REGRX.SON(TYPE != TYPE_WO);     //GROUP_REGRX.DESC
     end
     end
 
 
   always @(*)
   always @(*)
     begin
     begin
          prdata_pre  = {32{1'b0}};
          prdata_pre  = {32{1'b0}};

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