| Line 15... |
Line 15... |
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----------------------------------------------
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----------------------------------------------
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-- Constants
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-- Constants
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----------------------------------------------
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----------------------------------------------
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constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
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constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
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constant MAIN_CLK : integer := 50;
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constant BAUD_RATE : integer := 9600; -- Bits per Second
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constant BAUD_RATE : integer := 9600; -- Bits per Second
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constant RST_LVL : std_logic := '1'; -- Active Level of Reset
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constant RST_LVL : std_logic := '1'; -- Active Level of Reset
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----------------------------------------------
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----------------------------------------------
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-- Signal Declaration
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-- Signal Declaration
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| Line 32... |
Line 33... |
-- Configuration signals
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-- Configuration signals
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signal par_en : std_logic;
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signal par_en : std_logic;
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-- uPC Interface
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-- uPC Interface
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signal tx_req : std_logic;
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signal tx_req : std_logic;
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signal tx_end : std_logic;
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signal tx_end : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_data : std_logic_vector(7 downto 0) := x"5A";
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signal rx_ready : std_logic;
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signal rx_ready : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_data : std_logic_vector(7 downto 0);
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-- Testbench Signals
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-- Testbench Signals
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signal uart_clk : std_logic := '0';
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signal uart_clk : std_logic := '0';
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| Line 58... |
Line 59... |
rx => data_from_transceiver, -- RS232 received serial data
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rx => data_from_transceiver, -- RS232 received serial data
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tx => data_to_transceiver, -- RS232 transmitted serial data
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tx => data_to_transceiver, -- RS232 transmitted serial data
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-- RS232/UART Configuration
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-- RS232/UART Configuration
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par_en => par_en, -- Parity bit enable
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par_en => par_en, -- Parity bit enable
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-- uPC Interface
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-- uPC Interface
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tx_req => tx_req, -- Request SEND of data
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tx_req => '1', -- Request SEND of data
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tx_end => tx_end, -- Data SENDED
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tx_end => tx_end, -- Data SENDED
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tx_data => tx_data, -- Data to transmit
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tx_data => tx_data, -- Data to transmit
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rx_ready => rx_ready, -- Received data ready to uPC read
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rx_ready => rx_ready, -- Received data ready to uPC read
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rx_data => rx_data -- Received data
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rx_data => rx_data -- Received data
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);
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);
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| Line 84... |
Line 85... |
uart_clk <= not uart_clk;
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uart_clk <= not uart_clk;
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end process;
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end process;
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-- Reset generation
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-- Reset generation
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rst <= RST_LVL, not RST_LVL after MAIN_CLK_PER*5;
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rst <= RST_LVL, not RST_LVL after MAIN_CLK_PER*5;
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data_from_transceiver <= data_to_transceiver;
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end Behavioral;
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end Behavioral;
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No newline at end of file
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No newline at end of file
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