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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [FETCH_IMMEDIATE.v] - Diff between revs 2 and 8
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Rev 8 |
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// FETCH_IMM8
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// FETCH_IMM8
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// - Fetch 8 bit immediate as operand 'B'
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// - Fetch 8 bit immediate as operand 'B'
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//
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//
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//
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//
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// 2009-2012 Robert Finch
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// 2009-2012 Robert Finch
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// robfinch[remove]@opencores.org
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// robfinch[remove]@finitron.ca
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// Stratford
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// Stratford
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// operation.
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// operation.
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// ============================================================================
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// ============================================================================
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//
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//
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FETCH_IMM8:
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FETCH_IMM8:
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begin
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begin
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`INITIATE_CODE_READ
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code_read();
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state <= FETCH_IMM8_ACK;
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state <= FETCH_IMM8_ACK;
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end
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end
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FETCH_IMM8_ACK:
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FETCH_IMM8_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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lock_o <= bus_locked;
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lock_o <= bus_locked;
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b <= {{8{dat_i[7]}},dat_i};
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b <= {{8{dat_i[7]}},dat_i};
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state <= EXECUTE;
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state <= EXECUTE;
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end
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end
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FETCH_IMM16:
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FETCH_IMM16:
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begin
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begin
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lock_o <= 1'b1;
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lock_o <= 1'b1;
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`INITIATE_CODE_READ
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code_read();
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state <= FETCH_IMM16_ACK;
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state <= FETCH_IMM16_ACK;
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end
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end
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FETCH_IMM16_ACK:
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FETCH_IMM16_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`PAUSE_CODE_READ
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pause_code_read();
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state <= FETCH_IMM16a;
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state <= FETCH_IMM16a;
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b[ 7:0] <= dat_i;
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b[ 7:0] <= dat_i;
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end
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end
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FETCH_IMM16a:
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FETCH_IMM16a:
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begin
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begin
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`CONTINUE_CODE_READ
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continue_code_read();
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state <= FETCH_IMM16a_ACK;
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state <= FETCH_IMM16a_ACK;
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end
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end
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FETCH_IMM16a_ACK:
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FETCH_IMM16a_ACK:
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if (ack_i) begin
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if (ack_i) begin
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`TERMINATE_CODE_READ
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term_code_read();
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lock_o <= bus_locked;
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lock_o <= bus_locked;
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b[15:8] <= dat_i;
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b[15:8] <= dat_i;
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$display("Fetched #%h", {dat_i,b[7:0]});
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$display("Fetched #%h", {dat_i,b[7:0]});
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state <= EXECUTE;
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state <= EXECUTE;
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end
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end
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