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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// rtfSpriteController2.v
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// rtfSpriteController2.v
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`define ABITS 31:0
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`define ABITS 31:0
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// The cycle at which it's safe to update the working count and address.
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// The cycle at which it's safe to update the working count and address.
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// A good value is just before the end of the scan, but that depends on
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// A good value is just before the end of the scan, but that depends on
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// display resolution.
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// display resolution.
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`define SPR_WCA 12'd638
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`define SPR_WCA 12'd638
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//`define SUPPORT_LOWRES 1'b1
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module rtfSpriteController2(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
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module rtfSpriteController2(clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
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m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_sel_o, m_adr_o, m_dat_i,
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m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_sel_o, m_adr_o, m_dat_i, m_spriteno_o,
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dot_clk_i, hsync_i, vsync_i, zrgb_i, zrgb_o, test
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dot_clk_i, hsync_i, vsync_i, border_i, zrgb_i, zrgb_o, test
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);
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);
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// Bus slave port
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// Bus slave port
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input rst_i;
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input clk_i;
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input clk_i;
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input cs_i;
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input cs_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output ack_o;
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output ack_o;
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output m_stb_o;
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output m_stb_o;
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input m_ack_i;
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input m_ack_i;
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output [7:0] m_sel_o;
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output [7:0] m_sel_o;
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output reg [`ABITS] m_adr_o;
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output reg [`ABITS] m_adr_o;
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input [63:0] m_dat_i;
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input [63:0] m_dat_i;
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output reg [4:0] m_spriteno_o;
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// Video port
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// Video port
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input dot_clk_i;
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input dot_clk_i;
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input vsync_i;
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input vsync_i;
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input hsync_i;
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input hsync_i;
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input border_i;
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input [31:0] zrgb_i;
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input [31:0] zrgb_i;
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output reg [31:0] zrgb_o;
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output reg [31:0] zrgb_o;
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input test;
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input test;
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parameter NSPR = 32;
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parameter NSPR = 32;
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parameter IDLE = 3'd0;
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parameter IDLE = 2'd0;
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parameter DATA_FETCH = 3'd1;
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parameter DATA_FETCH = 2'd1;
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parameter MEM_ACCESS = 3'd2;
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parameter MEM_ACCESS = 2'd2;
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parameter WAIT_NACK = 3'd3;
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parameter NEXT_SPRITE = 3'd4;
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integer n;
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integer n;
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reg controller_enable;
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reg controller_enable = 1'b1;
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wire vclk;
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wire vclk;
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reg [2:0] state;
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reg [1:0] state = IDLE;
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reg [1:0] lowres;
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reg [1:0] lowres = 2'b00;
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wire [5:0] flashcnt;
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wire [5:0] flashcnt;
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reg rst_collision;
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reg rst_collision = 1'b0;
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reg [31:0] collision, c_collision;
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reg [31:0] collision, c_collision;
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reg [4:0] spriteno;
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reg [4:0] spriteno = 5'd0;
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reg sprite;
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reg sprite;
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reg [31:0] spriteEnable;
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reg [31:0] spriteEnable = 32'hFFFFFFFF;
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reg [31:0] spriteActive;
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reg [31:0] spriteActive;
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reg [11:0] sprite_pv [0:31];
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reg [11:0] sprite_pv [0:31];
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reg [11:0] sprite_ph [0:31];
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reg [11:0] sprite_ph [0:31];
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reg [3:0] sprite_pz [0:31];
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reg [3:0] sprite_pz [0:31];
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(* ram_style="distributed" *)
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(* ram_style="distributed" *)
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reg [`ABITS] spriteWaddr [0:31];
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reg [`ABITS] spriteWaddr [0:31];
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reg [15:0] spriteMcnt [0:31];
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reg [15:0] spriteMcnt [0:31];
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reg [15:0] spriteWcnt [0:31];
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reg [15:0] spriteWcnt [0:31];
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reg [63:0] m_spriteBmp [0:31];
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reg [63:0] m_spriteBmp [0:31];
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reg [63:0] spriteBmp [0:31];
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reg [63:0] spriteBmp [0:31];
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reg [31:0] spriteLink1;
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reg [31:0] spriteLink1 = 32'h0;
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reg [7:0] spriteColorNdx [0:31];
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reg [7:0] spriteColorNdx [0:31];
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initial begin
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initial begin
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for (n = 0; n < 256; n = n + 1) begin
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for (n = 0; n < 256; n = n + 1) begin
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sprite_color[n] <= 38'h0000FF1F1F;
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sprite_color[n] <= {6'h00,8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0};
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// sprite_color[n][31:0] <= {8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0}; // <- doesn't work
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end
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end
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for (n = 0; n < 32; n = n + 1) begin
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for (n = 0; n < 32; n = n + 1) begin
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sprite_ph[n] <= 260 + n * 40;
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if (n < 16) begin
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sprite_pv[n] <= 41 + n * 20;
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sprite_ph[n] <= 400 + n * 32;
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sprite_pz[n] <= 8'h00;
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sprite_pv[n] <= 100 + n * 8;
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spriteMcnt[n] <= 60 * 32;
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end
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else begin
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sprite_ph[n] <= 400 + (n - 16) * 32;
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sprite_pv[n] <= 200 + n * 8;
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end
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sprite_pz[n] <= 8'h08;
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spriteMcnt[n] <= 80 * 32;
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spriteBmp[n] <= 64'hFFFFFFFFFFFFFFFF;
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spriteBmp[n] <= 64'hFFFFFFFFFFFFFFFF;
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spriteAddr[n] <= 32'h40000 + (n << 12);
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end
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end
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end
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end
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wire pe_hsync, pe_vsync;
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wire pe_hsync, pe_vsync;
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wire [11:0] hctr, vctr;
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wire [11:0] hctr, vctr;
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reg [11:0] m_hctr, m_vctr;
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reg [11:0] m_hctr, m_vctr;
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// Generate acknowledge signal
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reg cs;
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wire cs = cs_i & cyc_i & stb_i;
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reg we;
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reg rdy1,rdy2,rdy3;
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reg [7:0] sel;
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always @(posedge clk_i)
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reg [11:0] adr;
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rdy1 <= cs;
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reg [63:0] dat;
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always @(posedge clk_i)
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rdy2 <= rdy1 & cs;
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wire clk;
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always @(posedge clk_i)
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`ifdef USE_CLOCK_GATE
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rdy3 <= rdy2 & cs;
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BUFH uclk (.I(clk_i), .O(clk));
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assign ack_o = (cs & we_i) ? 1'b1 : rdy3;
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`else
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wire clk = clk_i;
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`endif
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always @(posedge clk)
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cs <= cs_i & cyc_i & stb_i;
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always @(posedge clk)
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we <= we_i;
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always @(posedge clk)
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sel <= sel_i;
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always @(posedge clk)
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adr <= adr_i;
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always @(posedge clk)
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dat <= dat_i;
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ack_gen #(
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.READ_STAGES(4),
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.WRITE_STAGES(0),
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.REGISTER_OUTPUT(1)
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) uag1
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(
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.clk_i(clk),
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.ce_i(1'b1),
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.i(cs),
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.we_i(cs & we),
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.o(ack_o)
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);
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(* ram_style="block" *)
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(* ram_style="block" *)
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reg [63:0] shadow_ram [0:511];
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reg [63:0] shadow_ram [0:511];
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reg [63:0] shadow_ramo;
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reg [8:0] sradr;
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reg [8:0] sradr;
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always @(posedge clk_i)
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always @(posedge clk)
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if (cs & we_i) begin
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if (cs & we) begin
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if (sel_i[0]) shadow_ram[adr_i[11:3]][ 7: 0] <= dat_i;
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if (|sel[1:0]) shadow_ram[adr[11:3]][15: 0] <= dat[15: 0];
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if (sel_i[1]) shadow_ram[adr_i[11:3]][15: 8] <= dat_i;
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if (|sel[3:2]) shadow_ram[adr[11:3]][31:16] <= dat[31:16];
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if (sel_i[2]) shadow_ram[adr_i[11:3]][23:16] <= dat_i;
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if (|sel[5:4]) shadow_ram[adr[11:3]][47:32] <= dat[47:32];
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if (sel_i[3]) shadow_ram[adr_i[11:3]][31:24] <= dat_i;
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if (|sel[7:6]) shadow_ram[adr[11:3]][63:48] <= dat[63:48];
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if (sel_i[4]) shadow_ram[adr_i[11:3]][39:32] <= dat_i;
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end
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if (sel_i[5]) shadow_ram[adr_i[11:3]][47:40] <= dat_i;
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always @(posedge clk)
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if (sel_i[6]) shadow_ram[adr_i[11:3]][55:48] <= dat_i;
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sradr <= adr[11:3];
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if (sel_i[7]) shadow_ram[adr_i[11:3]][63:56] <= dat_i;
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always @(posedge clk)
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end
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shadow_ramo <= shadow_ram[sradr];
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always @(posedge clk_i)
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always @(posedge clk)
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sradr <= adr_i[11:3];
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case(adr[11:3])
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always @(posedge clk_i)
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case(adr_i[11:3])
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9'b1010_0001_0: dat_o <= c_collision;
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9'b1010_0001_0: dat_o <= c_collision;
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default: dat_o <= shadow_ram[sradr];
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default: dat_o <= shadow_ramo;
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endcase
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endcase
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always @(posedge clk_i)
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always @(posedge clk)
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if (rst_i) begin
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begin
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rst_collision <= `FALSE;
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controller_enable <= `TRUE;
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spriteEnable <= 32'hFFFFFFFF;
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spriteLink1 <= 32'h0;
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end
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else begin
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rst_collision <= `FALSE;
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rst_collision <= `FALSE;
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if (cs & we_i) begin
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if (cs & we) begin
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casez(adr_i[11:3])
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casez(adr[11:3])
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9'b0???_????_?: sprite_color[adr_i[10:3]] <= dat_i[37:0];
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9'b0???_????_?: sprite_color[adr[10:3]] <= dat[37:0];
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9'b100?_????_0: spriteAddr[adr_i[8:4]] <= dat_i[`ABITS];
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9'b100?_????_0: spriteAddr[adr[8:4]] <= dat[`ABITS];
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9'b100?_????_1:
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9'b100?_????_1:
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begin
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begin
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if (|sel_i[1:0]) sprite_ph[adr_i[8:4]] <= dat_i[11: 0];
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if (|sel[1:0]) sprite_ph[adr[8:4]] <= dat[11: 0];
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if (|sel_i[3:2]) sprite_pv[adr_i[8:4]] <= dat_i[27:16];
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if (|sel[3:2]) sprite_pv[adr[8:4]] <= dat[27:16];
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if ( sel_i[ 4]) sprite_pz[adr_i[8:4]] <= dat_i[39:32];
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if (|sel[5:4]) sprite_pz[adr[8:4]] <= dat[39:32];
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if (|sel_i[7:6]) spriteMcnt[adr_i[8:4]] <= dat_i[63:48];
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if (|sel[7:6]) spriteMcnt[adr[8:4]] <= dat[63:48];
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end
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end
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9'b1010_0000_0: spriteEnable <= dat_i[31:0];
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9'b1010_0000_0: spriteEnable <= dat[31:0];
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9'b1010_0000_1: spriteLink1 <= dat_i[31:0];
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9'b1010_0000_1: spriteLink1 <= dat[31:0];
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9'b1010_0001_0: rst_collision <= `TRUE;
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9'b1010_0001_0: rst_collision <= `TRUE;
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9'b1010_0001_1:
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9'b1010_0001_1:
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begin
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begin
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lowres <= dat_i[1:0];
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lowres <= dat[1:0];
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controller_enable <= dat_i[8];
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controller_enable <= dat[8];
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end
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end
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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assign m_stb_o = m_cyc_o;
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assign m_stb_o = m_cyc_o;
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assign m_sel_o = 8'hFF;
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assign m_sel_o = 8'hFF;
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wire clkm;
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`ifdef USE_CLOCK_GATE
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BUFHCE uclkm (.I(m_clk_i), .CE(controller_enable), .O(clkm));
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`else
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wire clkm = m_clk_i;
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`endif
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// Register hctr to m_clk_i domain
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// Register hctr to m_clk_i domain
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always @(posedge m_clk_i)
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always @(posedge clkm)
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m_hctr <= hctr;
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m_hctr <= hctr;
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// State machine
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// State machine
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always @(posedge m_clk_i)
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always @(posedge clkm)
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if (rst_i)
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state <= IDLE;
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else begin
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case(state)
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case(state)
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IDLE:
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IDLE:
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// dot_clk_i is likely faster than m_clk_i, so check for a trigger zone.
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// dot_clk_i is likely faster than m_clk_i, so check for a trigger zone.
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if (m_hctr < 12'd10 && controller_enable)
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if (m_hctr < 12'd10 && controller_enable)
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state <= DATA_FETCH;
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state <= DATA_FETCH;
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DATA_FETCH:
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DATA_FETCH:
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if (spriteActive[spriteno])
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if (spriteActive[spriteno]) begin
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if (~m_ack_i)
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state <= MEM_ACCESS;
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state <= MEM_ACCESS;
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else
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end
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state <= NEXT_SPRITE;
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else if (spriteno==5'd31)
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state <= IDLE;
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MEM_ACCESS:
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MEM_ACCESS:
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if (m_ack_i)
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if (m_ack_i|test) begin
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state <= WAIT_NACK;
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WAIT_NACK:
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if (~m_ack_i)
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state <= NEXT_SPRITE;
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NEXT_SPRITE:
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if (spriteno==5'd31)
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if (spriteno==5'd31)
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state <= IDLE;
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state <= IDLE;
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else
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else
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state <= DATA_FETCH;
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state <= DATA_FETCH;
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endcase
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end
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end
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default: state <= IDLE;
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endcase
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always @(posedge m_clk_i)
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always @(posedge clkm)
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if (rst_i) begin
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m_cyc_o <= `LOW;
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spriteno <= 5'd0;
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end
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else begin
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case(state)
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case(state)
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IDLE:
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IDLE:
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spriteno <= 5'd0;
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m_cyc_o <= `LOW;
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DATA_FETCH:
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DATA_FETCH:
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if (spriteActive[spriteno]) begin
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if (!m_ack_i && spriteActive[spriteno]) begin
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m_cyc_o <= `HIGH;
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m_cyc_o <= ~test;//`HIGH;
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m_adr_o <= spriteWaddr[spriteno];
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m_adr_o <= spriteWaddr[spriteno];
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m_spriteno_o <= spriteno;
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end
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end
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MEM_ACCESS:
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MEM_ACCESS:
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if (m_ack_i) begin
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if (m_ack_i|test) begin
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m_cyc_o <= `LOW;
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m_cyc_o <= `LOW;
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m_spriteBmp[spriteno] <= dat_i;
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m_spriteBmp[spriteno] <= m_dat_i;
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if (test)
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if (test)
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m_spriteBmp[spriteno] <= 64'h00005555AAAAFFFF;
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m_spriteBmp[spriteno] <= 64'h00005555AAAAFFFF;
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end
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end
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NEXT_SPRITE:
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default: ;
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endcase
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|
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always @(posedge clkm)
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case(state)
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IDLE:
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spriteno <= 5'd0;
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DATA_FETCH:
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if (!spriteActive[spriteno])
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spriteno <= spriteno + 5'd1;
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MEM_ACCESS:
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if (m_ack_i|test)
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spriteno <= spriteno + 5'd1;
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spriteno <= spriteno + 5'd1;
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default: ;
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endcase
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endcase
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end
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|
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// Register collision onto clk_i domain.
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// Register collision onto clk_i domain.
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always @(posedge clk_i)
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always @(posedge clk)
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c_collision <= collision;
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c_collision <= collision;
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|
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`ifdef USE_CLOCK_GATE
|
`ifdef USE_CLOCK_GATE
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BUFHCE ucb1
|
BUFHCE ucb1
|
(
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(
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| Line 266... |
Line 304... |
`endif
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`endif
|
|
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edge_det ued1 (.clk(vclk), .ce(1'b1), .i(hsync_i), .pe(pe_hsync), .ne(), .ee());
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edge_det ued1 (.clk(vclk), .ce(1'b1), .i(hsync_i), .pe(pe_hsync), .ne(), .ee());
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edge_det ued2 (.clk(vclk), .ce(1'b1), .i(vsync_i), .pe(pe_vsync), .ne(), .ee());
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edge_det ued2 (.clk(vclk), .ce(1'b1), .i(vsync_i), .pe(pe_vsync), .ne(), .ee());
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|
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VT163 #(12) uhctr (.clk(vclk), .clr_n(!rst_i), .ent(1'b1), .enp(1'b1), .ld_n(!pe_hsync), .d(12'd0), .q(hctr), .rco());
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VT163 #(12) uhctr (.clk(vclk), .clr_n(1'b1), .ent(1'b1), .enp(1'b1), .ld_n(!pe_hsync), .d(12'd0), .q(hctr), .rco());
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VT163 #(12) uvctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_hsync), .enp(1'b1), .ld_n(!pe_vsync), .d(12'd0), .q(vctr), .rco());
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VT163 #(12) uvctr (.clk(vclk), .clr_n(1'b1), .ent(pe_hsync), .enp(1'b1), .ld_n(!pe_vsync), .d(12'd0), .q(vctr), .rco());
|
VT163 # (6) ufctr (.clk(vclk), .clr_n(!rst_i), .ent(pe_vsync), .enp(1'b1), .ld_n(1'b1), .d( 6'd0), .q(flashcnt), .rco());
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VT163 # (6) ufctr (.clk(vclk), .clr_n(1'b1), .ent(pe_vsync), .enp(1'b1), .ld_n(1'b1), .d( 6'd0), .q(flashcnt), .rco());
|
|
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always @(posedge vclk)
|
always @(posedge vclk)
|
begin
|
begin
|
if (rst_collision)
|
if (rst_collision)
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collision <= 32'd0;
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collision <= 32'd0;
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| Line 323... |
Line 361... |
// Increment working count and address
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// Increment working count and address
|
|
|
reg [31:0] spriteShift;
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reg [31:0] spriteShift;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
begin
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spriteShift[n] <= ((hctr >> lowres) >= sprite_ph[n]);
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spriteShift[n] <= `FALSE;
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case(lowres)
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2'd0,2'd3: if (hctr >= sprite_ph[n]) spriteShift[n] <= `TRUE;
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|
2'd1: if (hctr[11:1] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
|
|
2'd2: if (hctr[11:2] >= sprite_ph[n]) spriteShift[n] <= `TRUE;
|
|
endcase
|
|
end
|
|
|
|
always @(posedge vclk)
|
always @(posedge vclk)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
spriteActive[n] = (spriteWcnt[n] <= spriteMcnt[n]) && spriteEnable[n];
|
spriteActive[n] <= (spriteWcnt[n] <= spriteMcnt[n]) && spriteEnable[n];
|
|
|
always @(posedge vclk)
|
always @(posedge vclk)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
begin
|
spriteWcnt[n] <= ((vctr >> lowres) - sprite_pv[n]) * 16'd32;
|
case(lowres)
|
|
2'd0,2'd3: if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
|
|
2'd1: if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
|
|
2'd2: if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWcnt[n] <= 16'd0;
|
|
endcase
|
|
// The following assumes there are at least 640 clocks in a scan line.
|
|
if (hctr==`SPR_WCA) // must be after image data fetch
|
|
if (spriteActive[n])
|
|
case(lowres)
|
|
2'd0,2'd3: spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
|
|
2'd1: if (vctr[0]) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
|
|
2'd2: if (vctr[1:0]==2'b11) spriteWcnt[n] <= spriteWcnt[n] + 16'd32;
|
|
endcase
|
|
end
|
|
|
|
always @(posedge vclk)
|
always @(posedge vclk)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
begin
|
spriteWaddr[n] <= spriteAddr[n] + spriteWcnt[n][15:2];
|
case(lowres)
|
|
2'd0,2'd3: if ((vctr == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
|
|
2'd1: if ((vctr[11:1] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
|
|
2'd2: if ((vctr[11:2] == sprite_pv[n]) && (hctr == 12'h005)) spriteWaddr[n] <= spriteAddr[n];
|
|
endcase
|
|
if (hctr==`SPR_WCA) // must be after image data fetch
|
|
case(lowres)
|
|
2'd0,2'd3: spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
|
|
2'd1: if (vctr[0]) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
|
|
2'd2: if (vctr[1:0]==2'b11) spriteWaddr[n] <= spriteWaddr[n] + 32'd8;
|
|
endcase
|
|
end
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// clock edge #0
|
// clock edge #0
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Get the sprite display status
|
// Get the sprite display status
|
| Line 400... |
Line 405... |
if (hctr==12'h5)
|
if (hctr==12'h5)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
spriteBmp[n] <= m_spriteBmp[n];
|
spriteBmp[n] <= m_spriteBmp[n];
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
if (spriteShift[n])
|
if (spriteShift[n])
|
|
`ifdef SUPPORT_LOWRES
|
case(lowres)
|
case(lowres)
|
2'd0,2'd3: spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
2'd0,2'd3: spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
2'd1: if (hctr[0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
2'd1: if (hctr[0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
2'd2: if (&hctr[1:0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
2'd2: if (&hctr[1:0]) spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
endcase
|
endcase
|
|
`else
|
|
spriteBmp[n] <= {spriteBmp[n][61:0],2'h0};
|
|
`endif
|
end
|
end
|
|
|
always @(posedge vclk)
|
always @(posedge vclk)
|
for (n = 0; n < NSPR; n = n + 1)
|
for (n = 0; n < NSPR; n = n + 1)
|
if (spriteLink1[n])
|
if (spriteLink1[n])
|
| Line 421... |
Line 430... |
// Compute index into sprite color palette
|
// Compute index into sprite color palette
|
// If none of the sprites are linked, each sprite has it's own set of colors.
|
// If none of the sprites are linked, each sprite has it's own set of colors.
|
// If the sprites are linked once the colors are available in groups.
|
// If the sprites are linked once the colors are available in groups.
|
// If the sprites are linked twice they all share the same set of colors.
|
// If the sprites are linked twice they all share the same set of colors.
|
// Pipelining register
|
// Pipelining register
|
reg blank1, blank2, blank3, blank4;
|
reg border3, border4;
|
reg border1, border2, border3, border4;
|
|
reg any_sprite_on2, any_sprite_on3, any_sprite_on4;
|
reg any_sprite_on2, any_sprite_on3, any_sprite_on4;
|
reg [31:0] zrgb_i3, zrgb_i4;
|
reg [31:0] zrgb_i3, zrgb_i4;
|
reg [7:0] zb_i3, zb_i4;
|
reg [7:0] zb_i3, zb_i4;
|
reg [7:0] sprite_z1, sprite_z2, sprite_z3, sprite_z4;
|
reg [7:0] sprite_z1, sprite_z2, sprite_z3, sprite_z4;
|
reg [7:0] sprite_pzx;
|
reg [7:0] sprite_pzx;
|
| Line 470... |
Line 478... |
always @(posedge vclk)
|
always @(posedge vclk)
|
sprite_on_d2 <= sprite_on_d1;
|
sprite_on_d2 <= sprite_on_d1;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
any_sprite_on2 <= |sprite_on_d1;
|
any_sprite_on2 <= |sprite_on_d1;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
blank2 <= blank1;
|
|
always @(posedge vclk)
|
|
border2 <= border1;
|
|
always @(posedge vclk)
|
|
spriteColorOut2 <= sprite_color[spriteClrNdx];
|
spriteColorOut2 <= sprite_color[spriteClrNdx];
|
always @(posedge vclk)
|
always @(posedge vclk)
|
sprite_z2 <= sprite_z1;
|
sprite_z2 <= sprite_z1;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| Line 499... |
Line 503... |
always @(posedge vclk)
|
always @(posedge vclk)
|
zrgb_i3 <= zrgb_i;
|
zrgb_i3 <= zrgb_i;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
zb_i3 <= zrgb_i[31:24];
|
zb_i3 <= zrgb_i[31:24];
|
always @(posedge vclk)
|
always @(posedge vclk)
|
blank3 <= blank2;
|
border3 <= border_i;
|
always @(posedge vclk)
|
|
border3 <= border2;
|
|
always @(posedge vclk)
|
always @(posedge vclk)
|
spriteColorOut3 <= spriteColorOut2;
|
spriteColorOut3 <= spriteColorOut2;
|
|
|
reg [23:0] flashOut;
|
reg [23:0] flashOut;
|
wire [23:0] reverseVideoOut = spriteColorOut2[37] ? alphaOut ^ 24'hFFFFFF : alphaOut;
|
wire [23:0] reverseVideoOut = spriteColorOut2[37] ? alphaOut ^ 24'hFFFFFF : alphaOut;
|
| Line 524... |
Line 526... |
always @(posedge vclk)
|
always @(posedge vclk)
|
any_sprite_on4 <= any_sprite_on3;
|
any_sprite_on4 <= any_sprite_on3;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
zb_i4 <= zb_i3;
|
zb_i4 <= zb_i3;
|
always @(posedge vclk)
|
always @(posedge vclk)
|
blank4 <= blank3;
|
|
always @(posedge vclk)
|
|
border4 <= border3;
|
border4 <= border3;
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// clock edge #5
|
// clock edge #5
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// final output registration
|
// final output registration
|
|
|
always @(posedge dot_clk_i)
|
always @(posedge dot_clk_i)
|
case(any_sprite_on4 & controller_enable)
|
casez({border4,any_sprite_on4 & controller_enable})
|
1'b1: zrgb_o <= (zb_i4 < sprite_z4) ? zrgb_i4 : {sprite_z4,flashOut};
|
2'b01: zrgb_o <= (zb_i4 <= sprite_z4) ? zrgb_i4 : {sprite_z4,flashOut};
|
1'b0: zrgb_o <= zrgb_i4;
|
2'b00: zrgb_o <= zrgb_i4;
|
|
2'b1?: zrgb_o <= zrgb_i4;
|
endcase
|
endcase
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
