// ============================================================================
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// ============================================================================
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// (C) 2007,2013 Robert Finch
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// (C) 2007,2013 Robert Finch
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// All rights reserved.
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// All rights reserved.
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// robfinch@<remove>finitron.ca
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// robfinch@<remove>finitron.ca
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//
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//
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// edge_det.v
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// edge_det.v
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the <organization> nor the
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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// derived from this software without specific prior written permission.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Notes:
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// Notes:
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//
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//
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// Edge detector
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// Edge detector
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// This little core detects an edge (positive, negative, and
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// This little core detects an edge (positive, negative, and
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// either) in the input signal.
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// either) in the input signal.
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//
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//
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// Verilog 1995
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// Verilog 1995
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// ============================================================================
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// ============================================================================
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module edge_det(rst, clk, ce, i, pe, ne, ee);
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module edge_det(rst, clk, ce, i, pe, ne, ee);
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input rst; // reset
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input rst; // reset
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input clk; // clock
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input clk; // clock
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input ce; // clock enable
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input ce; // clock enable
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input i; // input signal
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input i; // input signal
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output pe; // positive transition detected
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output pe; // positive transition detected
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output ne; // negative transition detected
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output ne; // negative transition detected
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output ee; // either edge (positive or negative) transition detected
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output ee; // either edge (positive or negative) transition detected
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reg ed;
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reg ed;
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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ed <= 1'b0;
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ed <= 1'b0;
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else if (ce)
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else if (ce)
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ed <= i;
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ed <= i;
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assign pe = ~ed & i; // positive: was low and is now high
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assign pe = ~ed & i; // positive: was low and is now high
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assign ne = ed & ~i; // negative: was high and is now low
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assign ne = ed & ~i; // negative: was high and is now low
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assign ee = ed ^ i; // either: signal is now opposite to what it was
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assign ee = ed ^ i; // either: signal is now opposite to what it was
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endmodule
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endmodule
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