| Line 89... |
Line 89... |
input we_i, // write (this signal is used to qualify reads)
|
input we_i, // write (this signal is used to qualify reads)
|
output [7:0] dat_o, // data out
|
output [7:0] dat_o, // data out
|
//------------------------
|
//------------------------
|
input cs_i, // chip select
|
input cs_i, // chip select
|
input baud16x_ce, // baud rate clock enable
|
input baud16x_ce, // baud rate clock enable
|
|
input tri0 baud8x, // switches to mode baudX8
|
input clear, // clear reciever
|
input clear, // clear reciever
|
input rxd, // external serial input
|
input rxd, // external serial input
|
output reg data_present, // data present in fifo
|
output reg data_present, // data present in fifo
|
output reg frame_err, // framing error
|
output reg frame_err, // framing error
|
output reg overrun // receiver overrun
|
output reg overrun // receiver overrun
|
);
|
);
|
|
|
|
//0 - simple sampling at middle of symbol period
|
|
//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
|
|
parameter SamplerStyle = 0;
|
|
|
// variables
|
// variables
|
reg [3:0] rxdd; // synchronizer flops
|
|
reg [7:0] cnt; // sample bit rate counter
|
reg [7:0] cnt; // sample bit rate counter
|
reg [9:0] rx_data; // working receive data register
|
reg [9:0] rx_data; // working receive data register
|
reg state; // state machine
|
reg state; // state machine
|
reg wf; // buffer write
|
reg wf; // buffer write
|
reg [7:0] dat;
|
reg [7:0] dat;
|
|
|
|
wire isX8;
|
|
buf(isX8, baud8x);
|
|
reg modeX8;
|
|
|
assign ack_o = cyc_i & stb_i & cs_i;
|
assign ack_o = cyc_i & stb_i & cs_i;
|
assign dat_o = ack_o ? dat : 8'b0;
|
assign dat_o = ack_o ? dat : 8'b0;
|
|
|
// update data register
|
// update data register
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
| Line 115... |
Line 123... |
|
|
// on a read clear the data present status
|
// on a read clear the data present status
|
// but set the status when the data register
|
// but set the status when the data register
|
// is updated by the receiver
|
// is updated by the receiver
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (wf) data_present <= 1;
|
if (rst_i)
|
|
data_present <= 0;
|
|
else if (wf)
|
|
data_present <= 1;
|
else if (ack_o & ~we_i) data_present <= 0;
|
else if (ack_o & ~we_i) data_present <= 0;
|
|
|
|
|
// Three stage synchronizer to synchronize incoming data to
|
// Three stage synchronizer to synchronize incoming data to
|
// the local clock (avoids metastability).
|
// the local clock (avoids metastability).
|
always @(posedge clk_i)
|
reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops
|
rxdd <= {rxdd[2:0],rxd};
|
reg rxdsmp; // majority samples
|
|
reg rdxstart; // for majority style sample solid 3tik-wide sample
|
|
reg [1:0] rxdsum;
|
|
always @(posedge clk_i) begin
|
|
rxdd <= {rxdd[4:0],rxd};
|
|
if (SamplerStyle == 0) begin
|
|
rxdsmp <= rxdd[3];
|
|
rdxstart <= rxdd[4]&~rxdd[3];
|
|
end
|
|
else begin
|
|
rxdsum[1] <= rxdsum[0];
|
|
rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};
|
|
rxdsmp <= rxdsum[1];
|
|
rdxstart <= (rxdsum[1] == 2'b00) & ((rxdsum[1] == 2'b11));
|
|
end
|
|
end
|
|
|
|
`define CNT_FRAME (8'h97)
|
|
`define CNT_FINISH (8'h9D)
|
|
|
always @(posedge clk_i) begin
|
always @(posedge clk_i) begin
|
if (rst_i) begin
|
if (rst_i) begin
|
state <= `IDLE;
|
state <= `IDLE;
|
wf <= 1'b0;
|
wf <= 1'b0;
|
overrun <= 1'b0;
|
overrun <= 1'b0;
|
|
frame_err <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
|
|
// Clear write flag
|
// Clear write flag
|
wf <= 1'b0;
|
wf <= 1'b0;
|
|
|
if (clear) begin
|
if (clear) begin
|
wf <= 1'b0;
|
wf <= 1'b0;
|
state <= `IDLE;
|
state <= `IDLE;
|
overrun <= 1'b0;
|
overrun <= 1'b0;
|
|
frame_err <= 1'b0;
|
end
|
end
|
|
|
else if (baud16x_ce) begin
|
else if (baud16x_ce) begin
|
|
|
case (state)
|
case (state)
|
|
|
// Sit in the idle state until a start bit is
|
// Sit in the idle state until a start bit is
|
// detected.
|
// detected.
|
`IDLE:
|
`IDLE:
|
// look for start bit
|
// look for start bit
|
if (~rxdd[3])
|
if (rdxstart)
|
state <= `CNT;
|
state <= `CNT;
|
|
|
`CNT:
|
`CNT:
|
begin
|
begin
|
// End of the frame ?
|
// End of the frame ?
|
// - check for framing error
|
// - check for framing error
|
// - write data to read buffer
|
// - write data to read buffer
|
if (cnt==8'h97)
|
if (cnt==`CNT_FRAME)
|
begin
|
begin
|
frame_err <= ~rxdd[3];
|
frame_err <= ~rxdsmp;
|
|
overrun <= data_present;
|
if (!data_present)
|
if (!data_present)
|
wf <= 1'b1;
|
wf <= 1'b1;
|
else
|
state <= `IDLE;
|
overrun <= 1'b1;
|
|
end
|
end
|
// Switch back to the idle state a little
|
// Switch back to the idle state a little
|
// bit too soon.
|
// bit too soon.
|
if (cnt==8'h9D)
|
//if (cnt==`CNT_FINISH) begin
|
state <= `IDLE;
|
// state <= `IDLE;
|
|
//end
|
|
|
// On start bit check make sure the start
|
// On start bit check make sure the start
|
// bit is low, otherwise go back to the
|
// bit is low, otherwise go back to the
|
// idle state because it's a false start.
|
// idle state because it's a false start.
|
if (cnt==8'h07 && rxdd[3])
|
if (cnt==8'h07 && rxdsmp)
|
state <= `IDLE;
|
state <= `IDLE;
|
|
|
if (cnt[3:0]==4'h7)
|
if (cnt[3:0]==4'h7)
|
rx_data <= {rxdd[3],rx_data[9:1]};
|
rx_data <= {rxdsmp,rx_data[9:1]};
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
| Line 189... |
Line 221... |
|
|
|
|
// bit rate counter
|
// bit rate counter
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (baud16x_ce) begin
|
if (baud16x_ce) begin
|
if (state == `IDLE)
|
if (state == `IDLE) begin
|
cnt <= 0;
|
cnt <= modeX8;
|
else
|
modeX8 <= isX8;
|
cnt <= cnt + 1;
|
end
|
|
else begin
|
|
cnt[7:1] <= cnt[7:1] + cnt[0];
|
|
cnt[0] <= ~cnt[0] | (modeX8);
|
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
