| Line 1... |
Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2023 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// rfTextController.sv
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// rfTextController.sv
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| Line 48... |
Line 48... |
// horizontal sync pulses.
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// horizontal sync pulses.
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//
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//
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// The core includes an embedded dual port RAM to hold the screen
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// The core includes an embedded dual port RAM to hold the screen
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// characters.
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// characters.
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//
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//
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// The controller expects a 128kB memory region to be reserved.
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// The controller expects a 256kB memory region to be reserved.
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//
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//
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// Memory Map:
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// Memory Map:
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// 00000-0FFFF display ram
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// 00000-3FFFF display ram
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// 10000-1FEFF character bitmap ram
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// 40000-7FFFF character bitmap ram
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// 1FF00-1FFFF controller registers
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// 80000-800FF controller registers
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//
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//
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Registers
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// Registers
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//
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//
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// 00h
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// 00h
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| Line 72... |
Line 72... |
// 15-12 hhhh pixel size - height
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// 15-12 hhhh pixel size - height
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// 21-16 nnnnnn char width in pixels
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// 21-16 nnnnnn char width in pixels
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// 24 r reset state bit
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// 24 r reset state bit
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// 32 e controller enable
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// 32 e controller enable
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// 40 m multi-color mode
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// 40 m multi-color mode
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// 41 a anti-alias mode
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// 48-52 nnnnn yscroll
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// 48-52 nnnnn yscroll
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// 56-60 nnnnn xscroll
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// 56-60 nnnnn xscroll
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// 10h
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// 10h
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// 30- 0 cccccccc cccccccc color code for transparent background RGB 4,9,9,9 (only RGB 7,7,7 used)
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// 30- 0 cccccccc cccccccc color code for transparent background RGB 4,9,9,9 (only RGB 7,7,7 used)
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// 63-32 cccc...cccc border color ZRGB 4,9,9,9
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// 63-32 cccc...cccc border color ZRGB 4,9,9,9
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| Line 98... |
Line 99... |
// 15- 0 aaaaaaaa aaaaaaaa font address in char bitmap memory
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// 15- 0 aaaaaaaa aaaaaaaa font address in char bitmap memory
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// 31-24 dddddd font ascent
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// 31-24 dddddd font ascent
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// 63-32 nnnnnnnn nnnnnnnn font ram lock "LOCK" or "UNLK"
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// 63-32 nnnnnnnn nnnnnnnn font ram lock "LOCK" or "UNLK"
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//
|
//
|
|
// 1209 LUTs / 1003 FFs / 48 BRAMs / 1 DSP
|
// ============================================================================
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// ============================================================================
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|
|
//`define USE_CLOCK_GATE
|
//`define USE_CLOCK_GATE
|
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//`define SUPPORT_AAM 1
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`define TC_RAM_ADDR 32'hEC000001
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`define TC_CBM_ADDR 32'hEC040001
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|
`define TC_REG_ADDR 32'hEC080001
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|
|
module rfTextController(
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module rfTextController(
|
rst_i, clk_i, cs_i,
|
rst_i, clk_i, cs_config_i, cs_io_i,
|
cti_i, cyc_i, stb_i, ack_o, wr_i, sel_i, adr_i, dat_i, dat_o,
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cti_i, cyc_i, stb_i, ack_o, wr_i, sel_i, adr_i, dat_i, dat_o,
|
dot_clk_i, hsync_i, vsync_i, blank_i, border_i, zrgb_i, zrgb_o, xonoff_i
|
dot_clk_i, hsync_i, vsync_i, blank_i, border_i, zrgb_i, zrgb_o, xonoff_i
|
);
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);
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parameter num = 4'd1;
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parameter num = 4'd1;
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parameter COLS = 8'd64;
|
parameter COLS = 8'd64;
|
parameter ROWS = 8'd32;
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parameter ROWS = 8'd32;
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parameter BUSWID = 64;
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parameter BUSWID = 32;
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parameter TEXT_CELL_COUNT = 8192;
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parameter CFG_BUS = 8'd0;
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parameter CFG_DEVICE = 5'd1;
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parameter CFG_FUNC = 3'd0;
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parameter CFG_VENDOR_ID = 16'h0;
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parameter CFG_DEVICE_ID = 16'h0;
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parameter CFG_SUBSYSTEM_VENDOR_ID = 16'h0;
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parameter CFG_SUBSYSTEM_ID = 16'h0;
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parameter CFG_ROM_ADDR = 32'hFFFFFFF0;
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|
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// Syscon
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// Syscon
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input rst_i; // reset
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input rst_i; // reset
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input clk_i; // clock
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input clk_i; // clock
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|
|
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input cs_config_i;
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input cs_io_i;
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|
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// Slave signals
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// Slave signals
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input cs_i; // circuit select
|
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input [2:0] cti_i;
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input [2:0] cti_i;
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input cyc_i; // valid bus cycle
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input cyc_i; // valid bus cycle
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input stb_i; // data strobe
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input stb_i; // data strobe
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output ack_o; // data acknowledge
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output ack_o; // data acknowledge
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input wr_i; // write
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input wr_i; // write
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input [BUSWID/8-1:0] sel_i; // byte lane select
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input [BUSWID/8-1:0] sel_i; // byte lane select
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input [16:0] adr_i; // address
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input [31:0] adr_i; // address
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input [BUSWID-1:0] dat_i; // data input
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input [BUSWID-1:0] dat_i; // data input
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output reg [BUSWID-1:0] dat_o; // data output
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output reg [BUSWID-1:0] dat_o; // data output
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|
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// Video signals
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// Video signals
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input dot_clk_i; // video dot clock
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input dot_clk_i; // video dot clock
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| Line 139... |
Line 155... |
input border_i; // border area
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input border_i; // border area
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input [39:0] zrgb_i; // input pixel stream
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input [39:0] zrgb_i; // input pixel stream
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output reg [39:0] zrgb_o; // output pixel stream
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output reg [39:0] zrgb_o; // output pixel stream
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input xonoff_i;
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input xonoff_i;
|
|
|
|
integer n2,n3;
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reg controller_enable;
|
reg controller_enable;
|
reg [39:0] bkColor40, bkColor40d, bkColor40d2; // background color
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reg [39:0] bkColor40, bkColor40d, bkColor40d2, bkColor40d3; // background color
|
reg [39:0] fgColor40, fgColor40d, fgColor40d2; // foreground color
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reg [39:0] fgColor40, fgColor40d, fgColor40d2, fgColor40d3; // foreground color
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|
|
wire [1:0] pix; // pixel value from character generator 1=on,0=off
|
wire [1:0] pix; // pixel value from character generator 1=on,0=off
|
|
|
reg por;
|
reg por;
|
wire vclk;
|
wire vclk;
|
assign txt_clk_o = vclk;
|
|
assign txt_we_o = por;
|
|
assign txt_sel_o = 8'hFF;
|
|
assign cbm_clk_o = vclk;
|
|
assign cbm_we_o = 1'b0;
|
|
assign cbm_sel_o = 8'hFF;
|
|
|
|
reg [63:0] rego;
|
reg [63:0] rego;
|
reg [5:0] yscroll;
|
reg [5:0] yscroll;
|
reg [5:0] xscroll;
|
reg [5:0] xscroll;
|
reg [11:0] windowTop;
|
reg [11:0] windowTop;
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| Line 178... |
Line 189... |
reg [ 2:0] rBlink;
|
reg [ 2:0] rBlink;
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reg [31:0] bdrColor; // Border color
|
reg [31:0] bdrColor; // Border color
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reg [ 3:0] pixelWidth; // horizontal pixel width in clock cycles
|
reg [ 3:0] pixelWidth; // horizontal pixel width in clock cycles
|
reg [ 3:0] pixelHeight; // vertical pixel height in scan lines
|
reg [ 3:0] pixelHeight; // vertical pixel height in scan lines
|
reg mcm; // multi-color mode
|
reg mcm; // multi-color mode
|
|
reg aam; // anti-alias mode
|
|
|
wire [11:0] hctr; // horizontal reference counter (counts clocks since hSync)
|
wire [11:0] hctr; // horizontal reference counter (counts clocks since hSync)
|
wire [11:0] scanline; // scan line
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wire [11:0] scanline; // scan line
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reg [ 7:0] row; // vertical reference counter (counts rows since vSync)
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reg [ 7:0] row; // vertical reference counter (counts rows since vSync)
|
reg [ 7:0] col; // horizontal column
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reg [ 7:0] col; // horizontal column
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| Line 210... |
Line 222... |
reg [30:0] tileColor2;
|
reg [30:0] tileColor2;
|
reg bgt, bgtd, bgtd2;
|
reg bgt, bgtd, bgtd2;
|
|
|
wire [63:0] tdat_o;
|
wire [63:0] tdat_o;
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wire [63:0] chdat_o;
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wire [63:0] chdat_o;
|
|
reg [63:0] cfg_dat [0:31];
|
|
reg [63:0] cfg_out;
|
|
|
|
function [63:0] fnRbo;
|
|
input n;
|
|
input [63:0] i;
|
|
fnRbo = n ? {i[7:0],i[15:8],i[23:16],i[31:24],i[39:32],i[47:40],i[55:48],i[63:56]} : i;
|
|
endfunction
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
// bus interfacing
|
// bus interfacing
|
// Address Decoding
|
// Address Decoding
|
// I/O range Dx
|
// I/O range Dx
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
// Register the inputs
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// Register the inputs
|
|
reg cs_config;
|
reg cs_rom, cs_reg, cs_text, cs_any;
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reg cs_rom, cs_reg, cs_text, cs_any;
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reg [16:0] radr_i;
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reg cs_rom1, cs_reg1, cs_text1;
|
|
reg cs_tc;
|
|
reg [17:0] radr_i;
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reg [63:0] rdat_i;
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reg [63:0] rdat_i;
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reg rwr_i;
|
reg rwr_i;
|
reg [7:0] rsel_i;
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reg [7:0] rsel_i;
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reg [7:0] wrs_i;
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reg [7:0] wrs_i;
|
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reg [31:0] tc_ram_addr;
|
|
reg [31:0] tc_cbm_addr;
|
|
reg [31:0] tc_reg_addr;
|
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
cs_rom <= cs_i && cyc_i && stb_i && (adr_i[16:8] >= 9'h100 && adr_i[16:8] < 9'h1FF);
|
cs_any <= cyc_i & stb_i & cs_io_i;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
cs_reg <= cs_i && cyc_i && stb_i && (adr_i[16:8] == 9'h1FF);
|
cs_config <= cyc_i & stb_i & cs_config_i && adr_i[27:20]==CFG_BUS && adr_i[19:15]==CFG_DEVICE && adr_i[14:12]==CFG_FUNC;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
cs_text <= cs_i && cyc_i && stb_i && (adr_i[16:8] < 9'h100);
|
cs_rom1 <= adr_i[31:18] == tc_cbm_addr[31:18];
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
cs_any <= cs_i && cyc_i && stb_i;
|
cs_reg1 <= adr_i[31: 8] == tc_reg_addr[31: 8];
|
|
always_ff @(posedge clk_i)
|
|
cs_text1 <= adr_i[31:18] == tc_ram_addr[31:18];
|
|
always_comb
|
|
cs_rom <= cs_rom1 && cs_any;
|
|
always_comb
|
|
cs_reg <= cs_reg1 && cs_any;
|
|
always_comb
|
|
cs_text <= cs_text1 && cs_any;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
wrs_i <= BUSWID==64 ? {8{wr_i}} & sel_i :
|
wrs_i <= (BUSWID==64) ? {8{wr_i}} & sel_i :
|
adr_i[2] ? {{4{wr_i}} & sel_i,4'h0} : {4'h0,{4{wr_i}} & sel_i};
|
adr_i[2] ? {{4{wr_i}} & sel_i,4'h0} : {4'h0,{4{wr_i}} & sel_i};
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
rwr_i <= wr_i;
|
rwr_i <= wr_i;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
rsel_i <= BUSWID==64 ? sel_i : adr_i[2] ? {sel_i,4'h0} : {4'h0,sel_i};
|
rsel_i <= (BUSWID==64) ? sel_i : adr_i[2] ? {sel_i,4'h0} : {4'h0,sel_i};
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
radr_i <= adr_i;
|
radr_i <= adr_i;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
rdat_i <= BUSWID==64 ? dat_i : {2{dat_i}};
|
rdat_i <= (BUSWID==64) ? dat_i : (BUSWID==32) ? {2{dat_i}} : {4{dat_i}};
|
|
|
// Register outputs
|
// Register outputs
|
always @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
if (BUSWID==64)
|
if (BUSWID==64)
|
casez({cs_rom,cs_reg,cs_text})
|
casez({cs_config,cs_rom,cs_reg,cs_text})
|
3'b1??: dat_o <= chdat_o;
|
4'b1???: dat_o <= cfg_out;
|
3'b01?: dat_o <= rego;
|
4'b01??: dat_o <= chdat_o;
|
3'b001: dat_o <= tdat_o;
|
4'b001?: dat_o <= rego;
|
|
4'b0001: dat_o <= tdat_o;
|
default: dat_o <= 'h0;
|
default: dat_o <= 'h0;
|
endcase
|
endcase
|
else if (BUSWID==32)
|
else if (BUSWID==32)
|
casez({cs_rom,cs_reg,cs_text})
|
casez({cs_config,cs_rom,cs_reg,cs_text})
|
3'b1??: dat_o <= radr_i[2] ? chdat_o[63:32] : chdat_o[31:0];
|
4'b1???: dat_o <= radr_i[2] ? cfg_out[63:32] : cfg_out[31:0];
|
3'b01?: dat_o <= radr_i[2] ? rego[63:32] : rego[31:0];
|
4'b01??: dat_o <= radr_i[2] ? chdat_o[63:32] : chdat_o[31:0];
|
3'b001: dat_o <= radr_i[2] ? tdat_o[63:32] : tdat_o[31:0];
|
4'b001?: dat_o <= radr_i[2] ? rego[63:32] : rego[31:0];
|
|
4'b0001: dat_o <= radr_i[2] ? tdat_o[63:32] : tdat_o[31:0];
|
default: dat_o <= 'd0;
|
default: dat_o <= 'd0;
|
endcase
|
endcase
|
else
|
else
|
dat_o <= 'd0;
|
dat_o <= 'd0;
|
|
|
| Line 278... |
Line 315... |
.READ_STAGES(5),
|
.READ_STAGES(5),
|
.WRITE_STAGES(1),
|
.WRITE_STAGES(1),
|
.REGISTER_OUTPUT(1)
|
.REGISTER_OUTPUT(1)
|
)
|
)
|
uag1 (
|
uag1 (
|
|
.rst_i(rst_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce_i(1'b1),
|
.ce_i(1'b1),
|
.i(cs_any),
|
.i((cs_any|cs_config) & ~rwr_i),
|
.we_i(cs_any & rwr_i),
|
.we_i((cs_any|cs_config) & rwr_i),
|
.o(ack_o),
|
.o(ack_o),
|
.rid_i(0),
|
.rid_i(0),
|
.wid_i(0),
|
.wid_i(0),
|
.rid_o(),
|
.rid_o(),
|
.wid_o()
|
.wid_o()
|
);
|
);
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
|
// config
|
|
//--------------------------------------------------------------------
|
|
|
|
initial begin
|
|
for (n3 = 0; n3 < 32; n3 = n3 + 1)
|
|
cfg_dat[n3] = 'd0;
|
|
end
|
|
|
|
always_ff @(posedge clk_i)
|
|
if (rst_i) begin
|
|
tc_ram_addr <= `TC_RAM_ADDR;
|
|
tc_cbm_addr <= `TC_CBM_ADDR;
|
|
tc_reg_addr <= `TC_REG_ADDR;
|
|
end
|
|
else begin
|
|
if (cs_config) begin
|
|
if (rwr_i)
|
|
case(radr_i[7:3])
|
|
5'h02:
|
|
begin
|
|
if (&rsel_i[3:0] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_ram_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[0]) tc_ram_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[1]) tc_ram_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[2]) tc_ram_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[3]) tc_ram_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
if (&rsel_i[7:4] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_cbm_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[4]) tc_cbm_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[5]) tc_cbm_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[6]) tc_cbm_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[7]) tc_cbm_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
end
|
|
5'h03:
|
|
begin
|
|
if (&rsel_i[3:0] && rdat_i[31:0]==32'hFFFFFFFF)
|
|
tc_reg_addr <= 32'hFFFFFFFF; // no memory is needed
|
|
else begin
|
|
if (rsel_i[0]) tc_reg_addr[7:0] <= rdat_i[7:0];
|
|
if (rsel_i[1]) tc_reg_addr[15:8] <= rdat_i[15:8];
|
|
if (rsel_i[2]) tc_reg_addr[23:16] <= rdat_i[23:16];
|
|
if (rsel_i[3]) tc_reg_addr[31:24] <= rdat_i[31:24];
|
|
end
|
|
end
|
|
default:
|
|
cfg_dat[radr_i[7:3]] <= rdat_i;
|
|
endcase
|
|
else
|
|
case(radr_i[7:3])
|
|
5'h00: cfg_out <= {32'h0,CFG_DEVICE_ID,CFG_VENDOR_ID};
|
|
5'h01: cfg_out <= {8'h00,8'h00,8'h00,8'd32,24'h0,8'h0};
|
|
5'h02: cfg_out <= {tc_cbm_addr,tc_ram_addr};
|
|
5'h03: cfg_out <= {32'hFFFFFFFF,tc_reg_addr};
|
|
5'h04: cfg_out <= 64'hFFFFFFFFFFFFFFFF;
|
|
5'h05: cfg_out <= {CFG_SUBSYSTEM_ID,CFG_SUBSYSTEM_VENDOR_ID,32'h0};
|
|
5'h06: cfg_out <= {24'h00,8'h00,CFG_ROM_ADDR};
|
|
5'h07: cfg_out <= {8'd8,8'd0,8'd0,8'd0,32'h0};
|
|
default: cfg_out <= cfg_dat[radr_i[7:3]];
|
|
endcase
|
|
end
|
|
end
|
|
|
|
|
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
`ifdef USE_CLOCK_GATE
|
`ifdef USE_CLOCK_GATE
|
BUFHCE ucb1 (.I(dot_clk_i), .CE(controller_enable), .O(vclk));
|
BUFHCE ucb1 (.I(dot_clk_i), .CE(controller_enable), .O(vclk));
|
`else
|
`else
|
assign vclk = dot_clk_i;
|
assign vclk = dot_clk_i;
|
| Line 397... |
Line 503... |
.we(rwr_i & rsel_i[7]),
|
.we(rwr_i & rsel_i[7]),
|
.i(rdat_i[63:56]),
|
.i(rdat_i[63:56]),
|
.o(rrm_o[63:56])
|
.o(rrm_o[63:56])
|
);
|
);
|
|
|
wire [31:0] lfsr1_o;
|
wire [26:0] lfsr1_o;
|
lfsr #(32) ulfsr1(rst_i, dot_clk_i, 1'b1, 1'b0, lfsr1_o);
|
lfsr27 #(.WID(27)) ulfsr1(rst_i, dot_clk_i, 1'b1, 1'b0, lfsr1_o);
|
wire [63:0] lfsr_o = {6'h20,
|
wire [63:0] lfsr_o = {6'h10,
|
lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
8'h00,lfsr1_o[8:0]
|
7'h00,lfsr1_o[8:0]
|
|
};
|
|
wire [63:0] lfsr_o2 = {6'h10,
|
|
// lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
|
// lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
|
4'b0,lfsr1_o[26:24],4'b0,lfsr1_o[23:21],lfsr1_o[20:18],4'b0,
|
|
4'b0,lfsr1_o[17:15],4'b0,lfsr1_o[14:12],lfsr1_o[11:9],4'b0,
|
|
7'h00,lfsr1_o[8:0]
|
|
};
|
|
wire [63:0] lfsr_o1 = {lfsr1_o[3:0],2'b00,
|
|
// lfsr1_o[26:24],4'b0,lfsr1_o[23:21],4'b0,lfsr1_o[20:18],4'b0,
|
|
// lfsr1_o[17:15],4'b0,lfsr1_o[14:12],4'b0,lfsr1_o[11:9],4'b0,
|
|
4'b0,lfsr1_o[26:24],4'b0,lfsr1_o[23:21],lfsr1_o[20:18],4'b0,
|
|
4'b0,lfsr1_o[17:15],lfsr1_o[14:12],4'b0,4'b0,lfsr1_o[11:9],
|
|
7'h00,lfsr1_o[8:0]
|
};
|
};
|
|
|
/* This snippit of code for performing burst accesses, under construction.
|
/* This snippit of code for performing burst accesses, under construction.
|
wire pe_cs;
|
wire pe_cs;
|
edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs_text), .pe(pe_cs), .ne(), .ee() );
|
edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs_text), .pe(pe_cs), .ne(), .ee() );
|
| Line 431... |
Line 551... |
*/
|
*/
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// text screen RAM
|
// text screen RAM
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
rfTextScreenRam screen_ram1
|
rfTextScreenRam #(
|
|
.TEXT_CELL_COUNT(TEXT_CELL_COUNT)
|
|
)
|
|
screen_ram1
|
(
|
(
|
.clka_i(clk_i),
|
.clka_i(clk_i),
|
.csa_i(cs_text),
|
.csa_i(cs_text),
|
.wea_i(rwr_i),
|
.wea_i(rwr_i),
|
.sela_i(rsel_i),
|
.sela_i(rsel_i),
|
.adra_i(radr_i[15:3]),
|
.adra_i(radr_i[16:3]),
|
.data_i(rdat_i),
|
.data_i(rdat_i),
|
.data_o(tdat_o),
|
.data_o(tdat_o),
|
.clkb_i(vclk),
|
.clkb_i(vclk),
|
.csb_i(ld_shft|por),
|
.csb_i(ld_shft|por),
|
.web_i(por),
|
.web_i(por),
|
.selb_i(8'hFF),
|
.selb_i(8'hFF),
|
.adrb_i(txtAddr[12:0]),
|
.adrb_i(txtAddr[13:0]),
|
.datb_i(lfsr_o),
|
.datb_i(lfsr_o),//txtAddr[12:0] > 13'd1664 ? lfsr_o1 : lfsr_o),
|
.datb_o(screen_ram_out)
|
.datb_o(screen_ram_out)
|
);
|
);
|
|
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// Character bitmap RAM
|
// Character bitmap RAM
|
| Line 502... |
Line 625... |
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
por <= 1'b1;
|
por <= 1'b1;
|
mcm <= 1'b0;
|
mcm <= 1'b0;
|
|
aam <= 1'b0;
|
controller_enable <= 1'b1;
|
controller_enable <= 1'b1;
|
xscroll <= 5'd0;
|
xscroll <= 5'd0;
|
yscroll <= 5'd0;
|
yscroll <= 5'd0;
|
txtTcCode <= 24'h1ff;
|
txtTcCode <= 24'h1ff;
|
bdrColor <= 32'hFFBF2020;
|
bdrColor <= 32'hFFBF2020;
|
startAddress <= 16'h0000;
|
startAddress <= 16'h0000;
|
fontAddress <= 16'h0000;
|
fontAddress <= 16'h0008;
|
font_locked <= 1'b1;
|
font_locked <= 1'b1;
|
fontAscent <= 6'd12;
|
fontAscent <= 6'd12;
|
cursorStart <= 5'd00;
|
cursorStart <= 5'd00;
|
cursorEnd <= 5'd31;
|
cursorEnd <= 5'd31;
|
cursorPos <= 16'h0003;
|
cursorPos <= 16'h0003;
|
| Line 533... |
Line 657... |
pixelHeight <= 4'd1; // 384 pixels
|
pixelHeight <= 4'd1; // 384 pixels
|
*/
|
*/
|
// 64x32
|
// 64x32
|
if (num==4'd1) begin
|
if (num==4'd1) begin
|
windowTop <= 12'd4058;//12'd16;
|
windowTop <= 12'd4058;//12'd16;
|
windowLeft <= 12'd3956;//12'd86;
|
windowLeft <= 12'd3918;//12'd3956;//12'd86;
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
pixelHeight <= 4'd0; // 600 pixels
|
numCols <= COLS;
|
numCols <= COLS;
|
numRows <= ROWS;
|
numRows <= ROWS;
|
maxRowScan <= 6'd17;
|
maxRowScan <= 6'd17;
|
maxScanpix <= 6'd11;
|
maxScanpix <= 6'd11;
|
rBlink <= 3'b111; // 01 = non display
|
rBlink <= 3'b111; // 01 = non display
|
charOutDelay <= 8'd7;
|
charOutDelay <= 8'd5;
|
end
|
end
|
else if (num==4'd2) begin
|
else if (num==4'd2) begin
|
windowTop <= 12'd4032;//12'd16;
|
windowTop <= 12'd4032;//12'd16;
|
windowLeft <= 12'd3720;//12'd86;
|
windowLeft <= 12'd3720;//12'd86;
|
pixelWidth <= 4'd0; // 800 pixels
|
pixelWidth <= 4'd0; // 800 pixels
|
| Line 583... |
Line 707... |
pixelWidth <= rdat_i[11:8]; // horizontal pixel width
|
pixelWidth <= rdat_i[11:8]; // horizontal pixel width
|
end
|
end
|
if (rsel_i[2]) maxScanpix <= rdat_i[20:16];
|
if (rsel_i[2]) maxScanpix <= rdat_i[20:16];
|
if (rsel_i[3]) por <= rdat_i[24];
|
if (rsel_i[3]) por <= rdat_i[24];
|
if (rsel_i[4]) controller_enable <= rdat_i[32];
|
if (rsel_i[4]) controller_enable <= rdat_i[32];
|
if (rsel_i[5]) mcm <= rdat_i[40];
|
if (rsel_i[5])
|
|
begin
|
|
mcm <= rdat_i[40];
|
|
aam <= rdat_i[41];
|
|
end
|
if (rsel_i[6]) yscroll <= rdat_i[52:48];
|
if (rsel_i[6]) yscroll <= rdat_i[52:48];
|
if (rsel_i[7]) xscroll <= rdat_i[60:56];
|
if (rsel_i[7]) xscroll <= rdat_i[60:56];
|
end
|
end
|
4'd2: // Color Control
|
4'd2: // Color Control
|
begin
|
begin
|
if (rsel_i[0]) txtTcCode[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) txtTcCode[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) txtTcCode[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) txtTcCode[15:8] <= rdat_i[15:8];
|
if (rsel_i[2]) txtTcCode[23:16] <= rdat_i[23:16];
|
if (rsel_i[2]) txtTcCode[23:16] <= rdat_i[23:16];
|
if (rsel_i[3]) txtTcCode[30:24] <= rdat_i[30:24];
|
if (rsel_i[3]) txtTcCode[30:24] <= rdat_i[30:24];
|
if (rsel_i[4]) bdrColor[7:0] <= dat_i[39:32];
|
if (rsel_i[4]) bdrColor[7:0] <= rdat_i[39:32];
|
if (rsel_i[5]) bdrColor[15:8] <= dat_i[47:40];
|
if (rsel_i[5]) bdrColor[15:8] <= rdat_i[47:40];
|
if (rsel_i[6]) bdrColor[23:16] <= dat_i[55:48];
|
if (rsel_i[6]) bdrColor[23:16] <= rdat_i[55:48];
|
if (rsel_i[7]) bdrColor[31:24] <= dat_i[63:56];
|
if (rsel_i[7]) bdrColor[31:24] <= rdat_i[63:56];
|
end
|
end
|
4'd3: // Color Control 2
|
4'd3: // Color Control 2
|
begin
|
begin
|
if (rsel_i[0]) tileColor1[7:0] <= rdat_i[7:0];
|
if (rsel_i[0]) tileColor1[7:0] <= rdat_i[7:0];
|
if (rsel_i[1]) tileColor1[15:8] <= rdat_i[15:8];
|
if (rsel_i[1]) tileColor1[15:8] <= rdat_i[15:8];
|
| Line 652... |
Line 780... |
// hardware cursors are really simple. More sophisticated hardware
|
// hardware cursors are really simple. More sophisticated hardware
|
// cursors can be had via the sprite controller.
|
// cursors can be had via the sprite controller.
|
//--------------------------------------------------------------------
|
//--------------------------------------------------------------------
|
|
|
reg [31:0] curout;
|
reg [31:0] curout;
|
integer n2;
|
wire [31:0] curout1;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft) begin
|
if (ld_shft) begin
|
curout = 'd0;
|
curout = 'd0;
|
case(cursorType)
|
case(cursorType)
|
// No cursor
|
// No cursor
|
| Line 692... |
Line 820... |
3'd7: curout = 32'hFFFFFFFF;
|
3'd7: curout = 32'hFFFFFFFF;
|
default: curout = 32'hFFFFFFFF;
|
default: curout = 32'hFFFFFFFF;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
ft_delay
|
|
#(
|
|
.WID(32),
|
|
.DEP(3)
|
|
)
|
|
uftd1
|
|
(
|
|
.clk(vclk),
|
|
.ce(ld_shft),
|
|
.i(curout),
|
|
.o(curout1)
|
|
);
|
|
|
//-------------------------------------------------------------
|
//-------------------------------------------------------------
|
// Video Stuff
|
// Video Stuff
|
//-------------------------------------------------------------
|
//-------------------------------------------------------------
|
|
|
wire pe_hsync;
|
wire pe_hsync;
|
| Line 852... |
Line 993... |
bcnt <= bcnt + 6'd1;
|
bcnt <= bcnt + 6'd1;
|
end
|
end
|
|
|
reg blink_en;
|
reg blink_en;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
blink_en <= (cursorPos+3==txtAddr);// && (rowscan[4:0] >= cursorStart) && (rowscan[4:0] <= cursorEnd);
|
blink_en <= (cursorPos+charOutDelay-2'd1==txtAddr);// && (rowscan[4:0] >= cursorStart) && (rowscan[4:0] <= cursorEnd);
|
|
|
VT151 ub2
|
VT151 ub2
|
(
|
(
|
.e_n(!blink_en),
|
.e_n(!blink_en),
|
.s(rBlink),
|
.s(rBlink),
|
| Line 871... |
Line 1012... |
bkColor40 <= {txtZorder1[5:2],txtBkCode1[20:14],5'b0,txtBkCode1[13:7],5'b0,txtBkCode1[6:0],5'b0};
|
bkColor40 <= {txtZorder1[5:2],txtBkCode1[20:14],5'b0,txtBkCode1[13:7],5'b0,txtBkCode1[6:0],5'b0};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bkColor40d <= bkColor40;
|
bkColor40d <= bkColor40;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (ld_shft)
|
bkColor40d2 <= bkColor40d;
|
bkColor40d2 <= bkColor40d;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
|
if (nhp)
|
|
bkColor40d3 <= bkColor40d2;
|
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
fgColor40 <= {txtZorder1[5:2],txtFgCode1[20:14],5'b0,txtFgCode1[13:7],5'b0,txtFgCode1[6:0],5'b0};
|
fgColor40 <= {txtZorder1[5:2],txtFgCode1[20:14],5'b0,txtFgCode1[13:7],5'b0,txtFgCode1[6:0],5'b0};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
fgColor40d <= fgColor40;
|
fgColor40d <= fgColor40;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (ld_shft)
|
fgColor40d2 <= fgColor40d;
|
fgColor40d2 <= fgColor40d;
|
|
always_ff @(posedge vclk)
|
|
if (nhp)
|
|
fgColor40d3 <= fgColor40d2;
|
|
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (ld_shft)
|
if (ld_shft)
|
bgt <= txtBkCode1=={txtTcCode[26:20],txtTcCode[17:11],txtTcCode[8:2]};
|
bgt <= txtBkCode1=={txtTcCode[26:20],txtTcCode[17:11],txtTcCode[8:2]};
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
| Line 896... |
Line 1043... |
bgtd2 <= bgtd;
|
bgtd2 <= bgtd;
|
|
|
// Convert character bitmap to pixels
|
// Convert character bitmap to pixels
|
reg [63:0] charout1;
|
reg [63:0] charout1;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
charout1 <= blink ? (char_bmp ^ curout) : char_bmp;
|
charout1 <= blink ? (char_bmp ^ curout1) : char_bmp;
|
|
|
// Convert parallel to serial
|
// Convert parallel to serial
|
rfTextShiftRegister ups1
|
rfTextShiftRegister ups1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(vclk),
|
.clk(vclk),
|
.mcm(mcm),
|
.mcm(mcm),
|
|
// .aam(aam),
|
.ce(nhp),
|
.ce(nhp),
|
.ld(ld_shft),
|
.ld(ld_shft),
|
.a(maxScanpix[5:0]),
|
.a(maxScanpix[5:0]),
|
.qin(2'b0),
|
.qin(2'b0),
|
.d(charout1),
|
.d(charout1),
|
| Line 922... |
Line 1070... |
wire bpix = hctr[2] ^ rowscan[4];// ^ blink;
|
wire bpix = hctr[2] ^ rowscan[4];// ^ blink;
|
always_ff @(posedge vclk)
|
always_ff @(posedge vclk)
|
if (nhp)
|
if (nhp)
|
iblank <= (row >= numRows) || (col >= numCols + charOutDelay) || (col < charOutDelay);
|
iblank <= (row >= numRows) || (col >= numCols + charOutDelay) || (col < charOutDelay);
|
|
|
|
`ifdef SUPPORT_AAM
|
|
function [11:0] fnBlendComponent;
|
|
input [11:0] c1;
|
|
input [11:0] c2;
|
|
input [1:0] pix;
|
|
case(pix)
|
|
2'b00: fnBlendComponent = c2;
|
|
2'b01: fnBlendComponent = ((c1 * 4'd5) + (c2 * 4'd11)) >> 4;
|
|
2'b10: fnBlendComponent = ((c1 * 4'd11) + (c2 * 4'd5)) >> 4;
|
|
2'b11: fnBlendComponent = c1;
|
|
endcase
|
|
endfunction
|
|
|
|
function [39:0] fnBlend;
|
|
input [39:0] c1;
|
|
input [39:0] c2;
|
|
input [1:0] pix;
|
|
fnBlend = {
|
|
|pix ? c1[39:36] : c2[39:36],
|
|
fnBlendComponent(c1[35:24],c2[35:24]),
|
|
fnBlendComponent(c1[23:12],c2[23:12]),
|
|
fnBlendComponent(c1[11: 0],c2[11: 0])
|
|
};
|
|
endfunction
|
|
`endif
|
|
|
// Choose between input RGB and controller generated RGB
|
// Choose between input RGB and controller generated RGB
|
// Select between foreground and background colours.
|
// Select between foreground and background colours.
|
// Note the ungated dot clock must be used here, or output from other
|
// Note the ungated dot clock must be used here, or output from other
|
// controllers would not be visible if the clock were gated off.
|
// controllers would not be visible if the clock were gated off.
|
always_ff @(posedge dot_clk_i)
|
always_ff @(posedge dot_clk_i)
|
casez({controller_enable&xonoff_i,blank_i,iblank,border_i,bpix,mcm,pix})
|
casez({controller_enable&xonoff_i,blank_i,iblank,border_i,bpix,mcm,aam,pix})
|
8'b01??????: zrgb_o <= 40'h00000000;
|
9'b01???????: zrgb_o <= 40'h00000000;
|
8'b11??????: zrgb_o <= 40'h00000000;
|
9'b11???????: zrgb_o <= 40'h00000000;
|
8'b1001????: zrgb_o <= {bdrColor[30:27],bdrColor[26:18],3'b0,bdrColor[17:9],3'b0,bdrColor[8:0],3'b0};
|
9'b1001?????: zrgb_o <= {bdrColor[30:27],bdrColor[26:18],3'b0,bdrColor[17:9],3'b0,bdrColor[8:0],3'b0};
|
8'b1000?00?: zrgb_o <= (zrgb_i[39:36] > bkColor40d2[39:36]) ? zrgb_i : bkColor40d2;
|
`ifdef SUPPORT_AAM
|
8'b1000?01?: zrgb_o <= fgColor40d2; // ToDo: compare z-order
|
9'b1000?01??: zrgb_o <= fnBlend(fgColor40d3,zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3, pix);
|
8'b1000?100: zrgb_o <= (zrgb_i[39:36] > bkColor40d2[39:36]) ? zrgb_i : bkColor40d2;
|
`endif
|
8'b1000?101: zrgb_o <= fgColor40d2;
|
9'b1000?000?: zrgb_o <= (zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3;
|
8'b1000?110: zrgb_o <= {tileColor1[30:27],tileColor1[26:18],3'b0,tileColor1[17:9],3'b0,tileColor1[8:0],3'b0};
|
9'b1000?001?: zrgb_o <= fgColor40d3; // ToDo: compare z-order
|
8'b1000?111: zrgb_o <= {tileColor2[30:27],tileColor2[26:18],3'b0,tileColor2[17:9],3'b0,tileColor2[8:0],3'b0};
|
9'b1000?1000: zrgb_o <= (zrgb_i[39:36] > bkColor40d3[39:36]) ? zrgb_i : bkColor40d3;
|
|
9'b1000?1001: zrgb_o <= fgColor40d3;
|
|
9'b1000?1010: zrgb_o <= {tileColor1[30:27],tileColor1[26:18],3'b0,tileColor1[17:9],3'b0,tileColor1[8:0],3'b0};
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9'b1000?1011: zrgb_o <= {tileColor2[30:27],tileColor2[26:18],3'b0,tileColor2[17:9],3'b0,tileColor2[8:0],3'b0};
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// 6'b1010?0: zrgb_o <= bgtd ? zrgb_i : bkColor32d;
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// 6'b1010?0: zrgb_o <= bgtd ? zrgb_i : bkColor32d;
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default: zrgb_o <= zrgb_i;
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default: zrgb_o <= zrgb_i;
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endcase
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endcase
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endmodule
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endmodule
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