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[/] [rtftextcontroller/] [trunk/] [rtl/] [verilog/] [rfTextScreenRam.sv] - Diff between revs 31 and 32

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2018-2022  Robert Finch, Waterloo
//   \\__/ o\    (C) 2018-2023  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//
//
Line 32... Line 32...
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
//
//
 
`define VENDOR_XILINX
 
 
module rfTextScreenRam(clka_i, csa_i, wea_i, sela_i, adra_i, data_i, data_o,
module rfTextScreenRam(clka_i, csa_i, wea_i, sela_i, adra_i, data_i, data_o,
        clkb_i, csb_i, web_i, selb_i, adrb_i, datb_i, datb_o);
        clkb_i, csb_i, web_i, selb_i, adrb_i, datb_i, datb_o);
input clka_i;
input clka_i;
input csa_i;
input csa_i;
input wea_i;
input wea_i;
input [7:0] sela_i;
input [7:0] sela_i;
input [15:3] adra_i;
input [16:3] adra_i;
input [63:0] data_i;
input [63:0] data_i;
output [63:0] data_o;
output [63:0] data_o;
input clkb_i;
input clkb_i;
input csb_i;
input csb_i;
input web_i;
input web_i;
input [7:0] selb_i;
input [7:0] selb_i;
input [15:3] adrb_i;
input [16:3] adrb_i;
input [63:0] datb_i;
input [63:0] datb_i;
output [63:0] datb_o;
output [63:0] datb_o;
 
parameter TEXT_CELL_COUNT = 16384;
 
localparam AWID = $clog2(TEXT_CELL_COUNT);
 
 
// xpm_memory_tdpram: True Dual Port RAM
// xpm_memory_tdpram: True Dual Port RAM
// Xilinx Parameterized Macro, version 2020.2
// Xilinx Parameterized Macro, version 2020.2
`ifdef VENDOR_XILINX
`ifdef VENDOR_XILINX
 
 
        xpm_memory_tdpram #(
        xpm_memory_tdpram #(
          .ADDR_WIDTH_A(13),
          .ADDR_WIDTH_A(AWID),
          .ADDR_WIDTH_B(13),
          .ADDR_WIDTH_B(AWID),
          .AUTO_SLEEP_TIME(0),
          .AUTO_SLEEP_TIME(0),
          .BYTE_WRITE_WIDTH_A(8),
          .BYTE_WRITE_WIDTH_A(8),
          .BYTE_WRITE_WIDTH_B(8),
          .BYTE_WRITE_WIDTH_B(8),
          .CASCADE_HEIGHT(0),
          .CASCADE_HEIGHT(0),
          .CLOCKING_MODE("independent_clock"), // String
          .CLOCKING_MODE("independent_clock"), // String
          .ECC_MODE("no_ecc"),            // String
          .ECC_MODE("no_ecc"),            // String
          .MEMORY_INIT_FILE("none"),                    // String
          .MEMORY_INIT_FILE("none"),                    // String
          .MEMORY_INIT_PARAM("0"),        // String
          .MEMORY_INIT_PARAM("0"),        // String
          .MEMORY_OPTIMIZATION("true"),   // String
          .MEMORY_OPTIMIZATION("true"),   // String
          .MEMORY_PRIMITIVE("block"),      // String
          .MEMORY_PRIMITIVE("block"),      // String
          .MEMORY_SIZE(524288),
          .MEMORY_SIZE(TEXT_CELL_COUNT*64),
          .MESSAGE_CONTROL(0),
          .MESSAGE_CONTROL(0),
          .READ_DATA_WIDTH_A(64),
          .READ_DATA_WIDTH_A(64),
          .READ_DATA_WIDTH_B(64),
          .READ_DATA_WIDTH_B(64),
          .READ_LATENCY_A(2),
          .READ_LATENCY_A(2),
          .READ_LATENCY_B(1),
          .READ_LATENCY_B(1),

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