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Simply RISC S1 Core - Functional Specification
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S1 Core - Functional Specification
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==============================================
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==================================
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Preface
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Preface
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The S1 is a CPU core that makes use of a single SPARC Core
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The S1 is a CPU core that makes use of a single SPARC Core
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extracted from the OpenSPARC T1, with the addition of a
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extracted from the OpenSPARC T1, with the addition of a
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Wishbone Bridge, a Reset Controller and an Interrupt
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Wishbone Bridge, a Reset Controller and an Interrupt
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Controller.
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Controller.
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___________________________________
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___________________________________
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| Simply RISC S1 Core |
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| S1 Core |
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| _______ _____ ________ ________ |
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| _______ _____ ________ ________ |
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|| || || || ||
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|| || || || ||
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|| Reset || Int || SPARC ||Wishbone||
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|| Reset || Int || SPARC ||Wishbone||
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|| Ctrl. ||Ctrl.|| Core || Bridge ||
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|| Ctrl. ||Ctrl.|| Core || Bridge ||
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|| || || || ||
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|| || || || ||
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The SPARC v9 ISA is obviously supported by the GCC compiler;
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The SPARC v9 ISA is obviously supported by the GCC compiler;
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also GNU/Linux is supported and the latest versions of the
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also GNU/Linux is supported and the latest versions of the
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kernel are ready for the T1.
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kernel are ready for the T1.
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There's also a complete GNU/Linux distribution, Ubuntu,
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There's also a complete GNU/Linux distribution, Ubuntu,
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that comes ready for the SPARC Core of the T1 and could be
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that comes ready for the SPARC Core of the T1 and could be
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used in a seamless way also for Simply RISC S1 based micros.
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used in a seamless way also for S1 based micros.
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S1 Memory Map
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S1 Memory Map
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-------------
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-------------
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The S1 Core has 64-bit wide Data Bus and Address Bus.
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The S1 Core has 64-bit wide Data Bus and Address Bus.
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Each bit of the Address Bus has a different meaning:
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Each bit of the Address Bus has a different meaning:
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