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https://opencores.org/ocsvn/s1_core/s1_core/trunk
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/*
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/*
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* Simply RISC S1 Testbench
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* S1 Testbench
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*
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*
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* (C) 2007 Simply RISC LLP
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* (C) 2007 Fabrizio Fazzino
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* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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*
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*
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* LICENSE:
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* version 2 as published by the Free Software Foundation.
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assign sys_irq = 64'b0;
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assign sys_irq = 64'b0;
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initial begin
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initial begin
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// Display start message
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// Display start message
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$display("INFO: TBENCH: Starting Simply RISC S1 Core simulation...");
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$display("INFO: TBENCH: Starting S1 Core simulation...");
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// Create VCD trace file
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// Create VCD trace file
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$dumpfile("trace.vcd");
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$dumpfile("trace.vcd");
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$dumpvars();
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$dumpvars();
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sys_clock <= 1'b1;
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sys_clock <= 1'b1;
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sys_reset <= 1'b1;
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sys_reset <= 1'b1;
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#1000
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#1000
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sys_reset <= 1'b0;
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sys_reset <= 1'b0;
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#49000
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#49000
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$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
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$display("INFO: TBENCH: Completed S1 Core simulation!");
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$finish;
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$finish;
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end
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end
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/*
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/*
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* Module instances
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* Module instances
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*/
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*/
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// Simply RISC S1 Core
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// S1 Core
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s1_top s1_top_0 (
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s1_top s1_top_0 (
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// System inputs
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// System inputs
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.sys_clock_i(sys_clock),
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.sys_clock_i(sys_clock),
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.sys_reset_i(sys_reset),
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.sys_reset_i(sys_reset),
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