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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company: (C) Athree, 2009
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// Company: (C) Athree, 2009
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// Engineer: Dmitry Rozhdestvenskiy
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// Engineer: Dmitry Rozhdestvenskiy
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// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
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// Email: dmitryr@a3.spb.ru divx4log@narod.ru
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//
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//
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// Design Name: Bridge from SPARC Core to Wishbone Master
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// Design Name: Bridge from SPARC Core to Wishbone Master
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// Module Name: os2wb
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// Module Name: os2wb
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// Project Name: SPARC SoC single-core
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// Project Name: SPARC SoC single-core
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//
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//
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