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`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

`ifdef FPGA_SYN

`define FPGA_SYN_ICD

`endif

    `ifdef FPGA_SYN_ALTERA

        reg     [11:2]          index_bf;

    `else

    `endif

    `ifdef FPGA_SYN_ALTERA

        reg [33:0]     icdata_ary_00_00  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_00_01  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_00_10  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_00_11  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_01_00  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_01_01  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_01_10  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_01_11  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_10_00  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_10_01  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_10_10  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_10_11  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_11_00  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_11_01  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_11_10  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

        reg [33:0]     icdata_ary_11_11  [255:0] /* synthesis syn_ramstyle = block_ram  */ ;/* syn_ramstyle = no_rw_check */

    `else

    `endif

    `ifdef FPGA_SYN_ALTERA

    `else

    `endif

//      assign index_bf = (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf : 

//              fdp_icd_index_bf);

    `SIMPLY_RISC_SCANIN,

        `ifdef FPGA_SYN_ALTERA

        `else

        `endif

    `ifdef FPGA_SYN_ALTERA

        reg [33:0] fetch_00_00_d;

        reg [33:0] fetch_00_01_d;

        reg [33:0] fetch_00_10_d;

        reg [33:0] fetch_00_11_d;

        reg [33:0] fetch_01_00_d;

        reg [33:0] fetch_01_01_d;

        reg [33:0] fetch_01_10_d;

        reg [33:0] fetch_01_11_d;

        reg [33:0] fetch_10_00_d;

        reg [33:0] fetch_10_01_d;

        reg [33:0] fetch_10_10_d;

        reg [33:0] fetch_10_11_d;

        reg [33:0] fetch_11_00_d;

        reg [33:0] fetch_11_01_d;

        reg [33:0] fetch_11_10_d;

        reg [33:0] fetch_11_11_d;

    reg        delay_half_cycle;

        always @(negedge clk) begin // Sandeep Changed this to negedge clock from posedge clock

        // Can we push the reads to the next negedge? Delay this read!! Looks

        // like the previous write does not get through

    `else

    `endif

      `ifdef FPGA_SYN_ALTERA

          index_f <= index_bf; // Sandeep moved this logic 1/2 cycle forward for altera

          index_bf <= (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf : // Moved this logic from a continuous assignment to a synchronous assignment

              fdp_icd_index_bf);

      `endif

`else

module bw_r_icd(/*AUTOARG*/

   // Outputs

   icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,

   icd_fuse_repair_en, so,

   // Inputs

   rclk, se, si, reset_l, sehold, fdp_icd_index_bf, ifq_icd_index_bf,

   fcl_icd_index_sel_ifq_bf, ifq_icd_wrway_bf, ifq_icd_worden_bf,

   ifq_icd_wrdata_i2, fcl_icd_rdreq_bf, fcl_icd_wrreq_bf,

   bist_ic_data, rst_tri_en, ifq_icd_data_sel_old_i2,

   ifq_icd_data_sel_fill_i2, ifq_icd_data_sel_bist_i2, fuse_icd_wren,

   fuse_icd_rid, fuse_icd_repair_value, fuse_icd_repair_en,

   efc_spc_fuse_clk1

   );

   input          rclk,

                  se,

                  si,

                  reset_l;

   input          sehold;

   input [11:2]   fdp_icd_index_bf,    // index to write to/read from

                  ifq_icd_index_bf;

   input          fcl_icd_index_sel_ifq_bf;

   input [1:0]    ifq_icd_wrway_bf;    // way to write to

   input [3:0]    ifq_icd_worden_bf;   // word to write to (ignore index 1:0)

   input [135:0]  ifq_icd_wrdata_i2;   // 128b data, 4b sw, 4b parity

   input          fcl_icd_rdreq_bf,

                              fcl_icd_wrreq_bf;

   input [7:0]    bist_ic_data;        // needs to be expanded

   input          rst_tri_en;

   // datain mux selects

   input          ifq_icd_data_sel_old_i2,

                  ifq_icd_data_sel_fill_i2,

                  ifq_icd_data_sel_bist_i2;

   // efuse values for redundancy

   input         fuse_icd_wren;

   input [3:0]   fuse_icd_rid;

   input [7:0]   fuse_icd_repair_value;

   input [1:0]   fuse_icd_repair_en;

   // efuse non ovl clks

   input         efc_spc_fuse_clk1;  // use this clk to talk to fuse hdr

   // outputs

   output [135:0]  icd_wsel_fetdata_s1,

                               icd_wsel_topdata_s1;

   // redundancy reg read

   output [7:0]    icd_fuse_repair_value;

   output [1:0]    icd_fuse_repair_en;

   output          so;

   //----------------------------------------------------------------------

   // Declarations

   //----------------------------------------------------------------------

   // local signals

`ifdef DEFINE_0IN

   reg [135:0]    fetdata_s1,

                  topdata_s1;

   wire [135:0]   fetdata_sa,

                  topdata_sa;

`else

   reg [33:0]     icdata_ary  [4095:0];

   reg [135:0]    fetdata_f,             // way0 is lsb, way3 is msb

                              topdata_f,

                  fetdata_sa,

                  topdata_sa,

                            fetdata_s1,

                              topdata_s1;

`endif

   wire           clk;

   wire [135:0]   next_wrdata_bf,

                  wrdata_f,

                  bist_data_expand;

   wire [11:2]     top_index,

                   index_bf;

   reg  [11:2]     index_f;

   wire [11:0]     wr_index0,

                               wr_index1,

                               wr_index2,

                               wr_index3;

   reg            rdreq_f,

                              wrreq_f;

   reg [3:0]      worden_f;

   reg [1:0]      wrway_f;

   // redundancy crap

   reg [7:0] red0_ev_row,

             red0_od_row;

   reg [9:0] red0_ev_col,

             red0_od_col;

   reg [7:0] red1_ev_row,

             red1_od_row;

   reg [9:0] red1_ev_col,

             red1_od_col;

   reg [7:0] red2_ev_row,

             red2_od_row;

   reg [9:0] red2_ev_col,

             red2_od_col;

   reg [7:0] red3_ev_row,

             red3_od_row;

   reg [9:0] red3_ev_col,

             red3_od_col;

   reg [7:0] icd_fuse_repair_value;

   reg [1:0] icd_fuse_repair_en;

   //

   // Code start here 

   //

   // clk header derives clk from rclk

   assign         clk = rclk;

   // mux merged with flop

   assign index_bf = fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :

                                                fdp_icd_index_bf;

   always @ (posedge clk)

     begin

              // input flops

        if (~sehold)

          begin

                   rdreq_f <= fcl_icd_rdreq_bf;

                   wrreq_f <= fcl_icd_wrreq_bf;

                   index_f <= index_bf;

                   wrway_f <= ifq_icd_wrway_bf;

                   worden_f <= ifq_icd_worden_bf;

          end

              // S stage flops (for rd data)

              fetdata_s1 <= fetdata_sa;

              topdata_s1 <= topdata_sa;

     end // always @ (posedge clk)

   // BIST data

   assign   bist_data_expand = {bist_ic_data[1:0], {4{bist_ic_data[7:0]}},

                                bist_ic_data[1:0], {4{bist_ic_data[7:0]}},

                                bist_ic_data[1:0], {4{bist_ic_data[7:0]}},

                                bist_ic_data[1:0], {4{bist_ic_data[7:0]}}};

   // Mux + flop for write data input

   // ic data enable mux

   mux3ds #(136) icden_mux(.dout (next_wrdata_bf),

                                             .in0  (wrdata_f),

                                             .in1  (ifq_icd_wrdata_i2),

                                             .in2  (bist_data_expand),

                                             .sel0 (ifq_icd_data_sel_old_i2),

                                             .sel1 (ifq_icd_data_sel_fill_i2),

                                             .sel2 (ifq_icd_data_sel_bist_i2));

   // write data regsiter

   // se hold is taken care of by external logic (in ifqctl)

   dffe_s #(136)  wrdata_reg(.din (next_wrdata_bf),

                                             .clk (clk),

                                             .q   (wrdata_f),

                           .en  (~sehold),

                                             .se  (se), `SIMPLY_RISC_SCANIN, .so());

   //----------------------------------------------------------------------

   // Read Operation

   //----------------------------------------------------------------------

   // The index has 2 parts. 

   //    1. The 16B half-line index -- bits 11:4

   //    2. The word offset -- bits 3:2 for reads, xx for writes

   //    3. The way -- wrway_f for writes, xx for reads

   // i.e. we read 1 word from each of 4 ways, but 

   //      we write 4 words to 1 way

   assign top_index = {index_f[11:3] , 1'b1};

`ifdef DEFINE_0IN

// physical implmentation: ignore this and use else portion

   wire [15:0] we_wrd = ({ 3'b0,worden_f[3], 3'b0,worden_f[2],

                           3'b0,worden_f[1], 3'b0,worden_f[0] }) << wrway_f;

   wire [543:0] we = (~wrreq_f        )   ? 544'h0 :

                { {34{we_wrd[15]}}, {34{we_wrd[14]}}, {34{we_wrd[13]}}, {34{we_wrd[12]}},

                  {34{we_wrd[11]}}, {34{we_wrd[10]}}, {34{we_wrd[ 9]}}, {34{we_wrd[ 8]}},

                  {34{we_wrd[ 7]}}, {34{we_wrd[ 6]}}, {34{we_wrd[ 5]}}, {34{we_wrd[ 4]}},

                  {34{we_wrd[ 3]}}, {34{we_wrd[ 2]}}, {34{we_wrd[ 1]}}, {34{we_wrd[ 0]}} };

   wire [543:0] din = ({ {4{wrdata_f[ 33: 0]}}, {4{wrdata_f[ 67: 34]}},

                         {4{wrdata_f[101:68]}}, {4{wrdata_f[135:102]}} });

   wire [543:0] dout;

   ic_data ic_data ( .nclk(~clk), .adr(index_f[11:4]), .we(we), .din(din), .dout(dout) );

   wire [271:0] dout_l1 = index_f[3] ? dout[543:272] : dout[271:0];

   assign       fetdata_sa[135:0] = index_f[2] ? dout_l1[271:136] : dout_l1[135:0];

   assign       topdata_sa[135:0] =              dout_l1[271:136];

`else

   // for physical implementation use this

   // read (inst[31:0] + sw bit + par bit) * 4 ways

   always @(/*AUTOSENSE*/ /*memory or*/ index_f or rdreq_f

            or top_index or wrreq_f)

     begin

        if (rdreq_f)

          begin

             if (wrreq_f)  // rd-wr contention

               begin

                        fetdata_f = 136'bx;

                        topdata_f = 136'bx;

                     end

                   else

                     begin  // regular read

                        fetdata_f[33:0] = icdata_ary[{index_f,2'b00}];    // way 0

                        fetdata_f[67:34] = icdata_ary[{index_f,2'b01}];   // way 1

                        fetdata_f[101:68] = icdata_ary[{index_f,2'b10}];  // way 2

                        fetdata_f[135:102] = icdata_ary[{index_f,2'b11}]; // way 3