| Line 65... |
Line 65... |
////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_IDCT
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`endif
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module bw_r_rf16x32 (/*AUTOARG*/
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module bw_r_rf16x32 (/*AUTOARG*/
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// Outputs
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// Outputs
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| Line 115... |
Line 115... |
//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// local signals
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// local signals
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wire [6:0] rd_index ;
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wire [6:0] rd_index ;
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// 512 bit array
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// 512 bit array
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`ifdef FPGA_SYN_IDCT
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reg [31:0] idcv_ary_0000;
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reg [31:0] idcv_ary_0000;
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reg [31:0] idcv_ary_0001;
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reg [31:0] idcv_ary_0001;
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reg [31:0] idcv_ary_0010;
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reg [31:0] idcv_ary_0010;
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reg [31:0] idcv_ary_0011;
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reg [31:0] idcv_ary_0011;
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reg [31:0] idcv_ary_0100;
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reg [31:0] idcv_ary_0100;
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| Line 132... |
Line 132... |
reg [31:0] idcv_ary_1011;
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reg [31:0] idcv_ary_1011;
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reg [31:0] idcv_ary_1100;
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reg [31:0] idcv_ary_1100;
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reg [31:0] idcv_ary_1101;
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reg [31:0] idcv_ary_1101;
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reg [31:0] idcv_ary_1110;
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reg [31:0] idcv_ary_1110;
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reg [31:0] idcv_ary_1111;
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reg [31:0] idcv_ary_1111;
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`else
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reg [511:0] idcv_ary;
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`endif
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reg [3:0] vbit,
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reg [3:0] vbit,
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vbit_sa;
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vbit_sa;
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reg [6:2] wr_index_d1;
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reg [6:2] wr_index_d1;
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| Line 147... |
Line 147... |
reg rdreq_d1,
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reg rdreq_d1,
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wrreq_d1;
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wrreq_d1;
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reg [15:0] bit_wen_d1;
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reg [15:0] bit_wen_d1;
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reg din_d1;
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reg din_d1;
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reg [4:0] index;
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wire rst_all;
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wire rst_all;
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Code Begins Here
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// Code Begins Here
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| Line 176... |
Line 177... |
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Read Operation
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// Read Operation
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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`ifdef FPGA_SYN_IDCT
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always @(/*AUTOSENSE*/
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always @(/*AUTOSENSE*/
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idcv_ary_0000 or idcv_ary_0001 or idcv_ary_0010 or idcv_ary_0011 or
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idcv_ary_0000 or idcv_ary_0001 or idcv_ary_0010 or idcv_ary_0011 or
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idcv_ary_0100 or idcv_ary_1001 or idcv_ary_1010 or idcv_ary_0111 or
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idcv_ary_0100 or idcv_ary_1001 or idcv_ary_1010 or idcv_ary_0111 or
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idcv_ary_1000 or idcv_ary_0101 or idcv_ary_0110 or idcv_ary_1011 or
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idcv_ary_1000 or idcv_ary_0101 or idcv_ary_0110 or idcv_ary_1011 or
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idcv_ary_1100 or idcv_ary_1101 or idcv_ary_1110 or idcv_ary_1111 or rd_index_d1 or rdreq_d1)
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idcv_ary_1100 or idcv_ary_1101 or idcv_ary_1110 or idcv_ary_1111 or rd_index_d1 or rdreq_d1)
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`else
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always @(/*AUTOSENSE*/idcv_ary or rd_index_d1 or rdreq_d1)
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`endif
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begin
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begin
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if (rdreq_d1) // should work even if there is read
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if (rdreq_d1) // should work even if there is read
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// write conflict. Data can be latest
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// write conflict. Data can be latest
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// or previous but should not be x
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// or previous but should not be x
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begin
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begin
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`ifdef FPGA_SYN_IDCT
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case(rd_index_d1[1:0])
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case(rd_index_d1[1:0])
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2'b00: begin
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2'b00: begin
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vbit[0] = idcv_ary_0000[{rd_index_d1[6:2]}];
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vbit[0] = idcv_ary_0000[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0001[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_0001[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0010[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_0010[{rd_index_d1[6:2]}];
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| Line 217... |
Line 218... |
vbit[1] = idcv_ary_1101[{rd_index_d1[6:2]}];
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vbit[1] = idcv_ary_1101[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1110[{rd_index_d1[6:2]}];
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vbit[2] = idcv_ary_1110[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1111[{rd_index_d1[6:2]}];
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vbit[3] = idcv_ary_1111[{rd_index_d1[6:2]}];
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end
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end
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endcase
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endcase
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`else
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vbit[0] = idcv_ary[{rd_index_d1, 2'b00}]; // way 0
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vbit[1] = idcv_ary[{rd_index_d1, 2'b01}]; // way 1
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vbit[2] = idcv_ary[{rd_index_d1, 2'b10}]; // way 2
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vbit[3] = idcv_ary[{rd_index_d1, 2'b11}]; // way 3
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`endif
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end // if (rdreq_d1)
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end // if (rdreq_d1)
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else // i/dcache disabled or rd disabled
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else // i/dcache disabled or rd disabled
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begin
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begin
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vbit[3:0] = 4'bx;
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vbit[3:0] = 4'bx;
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| Line 237... |
Line 238... |
// 12/06 modified to be
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// 12/06 modified to be
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// 0 0 0
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// 0 0 0
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// 0 1 X
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// 0 1 X
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// 1 0 0
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// 1 0 0
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// 1 1 1
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// 1 1 1
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`ifdef FPGA_SYN_IDCT
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initial
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begin
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for(index = 5'h0; index < 5'h1f; index = index+1)
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begin
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idcv_ary_0000[index] = 1'b0;
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idcv_ary_0001[index] = 1'b0;
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idcv_ary_0010[index] = 1'b0;
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idcv_ary_0011[index] = 1'b0;
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idcv_ary_0100[index] = 1'b0;
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idcv_ary_0101[index] = 1'b0;
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idcv_ary_0110[index] = 1'b0;
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idcv_ary_0111[index] = 1'b0;
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idcv_ary_1000[index] = 1'b0;
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idcv_ary_1001[index] = 1'b0;
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idcv_ary_1010[index] = 1'b0;
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idcv_ary_1011[index] = 1'b0;
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idcv_ary_1100[index] = 1'b0;
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idcv_ary_1101[index] = 1'b0;
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idcv_ary_1110[index] = 1'b0;
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idcv_ary_1111[index] = 1'b0;
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end
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end
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`endif
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reg [3:0] wr_data;
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reg [3:0] wr_data;
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always @ (/*AUTOSENSE*/bit_wen_d1 or rd_index_d1 or rst_all
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always @ (/*AUTOSENSE*/bit_wen_d1 or rd_index_d1 or rst_all
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or wr_index_d1 or wrreq_d1)
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or wr_index_d1 or wrreq_d1)
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begin
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begin
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if (rd_index_d1[6:2] == wr_index_d1[6:2])
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if (rd_index_d1[6:2] == wr_index_d1[6:2])
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| Line 253... |
Line 277... |
endcase // case(rd_index_d1[1:0])
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endcase // case(rd_index_d1[1:0])
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else
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else
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wr_data = 4'b0;
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wr_data = 4'b0;
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end
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end
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`ifdef FPGA_SYN_IDCT
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 :
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 :
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(~wr_data & vbit | wr_data & {4{din_d1}} & vbit);
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(~wr_data & vbit | wr_data & {4{din_d1}} & vbit);
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`else
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// SA latch -- to make 0in happy
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always @ (/*AUTOSENSE*/clk or din_d1 or vbit or wr_data)
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begin
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if (clk)
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begin
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vbit_sa <= (~wr_data & vbit |
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wr_data & {4{din_d1}} & (vbit | 4'bxxxx));
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end
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end
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// bug:2776 - remove holding the last read value
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// reset_l rdreq_d1 dout
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// 0 - 0
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// 1 0 0
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// 1 1 vbit_sa
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assign dout[3:0] = (~reset_l | ~rdreq_d1) ? 4'b0000 : vbit_sa[3:0] ;
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`endif
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Write Operation
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// Write Operation
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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| Line 293... |
Line 317... |
always @ (negedge clk)
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always @ (negedge clk)
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begin
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begin
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if (wrreq_d1 & ~rst_all) // should work even if rd-wr conflict
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if (wrreq_d1 & ~rst_all) // should work even if rd-wr conflict
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begin
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begin
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// line 0 (5:4=00)
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// line 0 (5:4=00)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[0]) idcv_ary_0000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[0]) idcv_ary_0000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[1]) idcv_ary_0001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[1]) idcv_ary_0001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[2]) idcv_ary_0010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[2]) idcv_ary_0010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[3]) idcv_ary_0011[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[3]) idcv_ary_0011[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[0])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b00}] = din_d1;
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if (bit_wen_d1[1])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b01}] = din_d1;
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if (bit_wen_d1[2])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b10}] = din_d1;
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if (bit_wen_d1[3])
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idcv_ary[{wr_index_d1[6:2],2'b00,2'b11}] = din_d1;
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`endif
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// line 1 (5:4=01)
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// line 1 (5:4=01)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[4]) idcv_ary_0100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[4]) idcv_ary_0100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[5]) idcv_ary_0101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[5]) idcv_ary_0101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[6]) idcv_ary_0110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[6]) idcv_ary_0110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[7]) idcv_ary_0111[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[7]) idcv_ary_0111[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[4])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b00}] = din_d1;
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if (bit_wen_d1[5])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b01}] = din_d1;
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if (bit_wen_d1[6])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b10}] = din_d1;
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if (bit_wen_d1[7])
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idcv_ary[{wr_index_d1[6:2],2'b01,2'b11}] = din_d1;
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`endif
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// line 2 (5:4=10)
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// line 2 (5:4=10)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[8]) idcv_ary_1000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[8]) idcv_ary_1000[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[9]) idcv_ary_1001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[9]) idcv_ary_1001[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[10]) idcv_ary_1010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[10]) idcv_ary_1010[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[11]) idcv_ary_1011[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[11]) idcv_ary_1011[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[8])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b00}] = din_d1;
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if (bit_wen_d1[9])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b01}] = din_d1;
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if (bit_wen_d1[10])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b10}] = din_d1;
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if (bit_wen_d1[11])
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idcv_ary[{wr_index_d1[6:2],2'b10,2'b11}] = din_d1;
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`endif
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// line 3 (5:4=11)
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// line 3 (5:4=11)
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`ifdef FPGA_SYN_IDCT
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if (bit_wen_d1[12]) idcv_ary_1100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[12]) idcv_ary_1100[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[13]) idcv_ary_1101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[13]) idcv_ary_1101[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[14]) idcv_ary_1110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[14]) idcv_ary_1110[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[15]) idcv_ary_1111[{wr_index_d1[6:2]}] = din_d1;
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if (bit_wen_d1[15]) idcv_ary_1111[{wr_index_d1[6:2]}] = din_d1;
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`else
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if (bit_wen_d1[12])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b00}] = din_d1;
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if (bit_wen_d1[13])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b01}] = din_d1;
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if (bit_wen_d1[14])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b10}] = din_d1;
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if (bit_wen_d1[15])
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idcv_ary[{wr_index_d1[6:2],2'b11,2'b11}] = din_d1;
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`endif
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end
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end
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end // always @ (...
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end // always @ (...
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// synopsys translate_off
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// synopsys translate_off
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Monitors, shadow logic and other stuff not directly related to
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// Monitors, shadow logic and other stuff not directly related to
|
// memory functionality
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// memory functionality
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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`ifdef INNO_MUXEX
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`else
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// Address monitor
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// Address monitor
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always @ (/*AUTOSENSE*/rd_index_d1 or rdreq_d1 or wr_index_d1
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always @ (/*AUTOSENSE*/rd_index_d1 or rdreq_d1 or wr_index_d1
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or wrreq_d1)
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or wrreq_d1)
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begin
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begin
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if (rdreq_d1 && (rd_index_d1 == 7'bX))
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if (rdreq_d1 && (rd_index_d1 == 7'bX))
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begin
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begin
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 read address X"
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 read address X"
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`ifdef DEFINE_0IN
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`else
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//$display("RFRDADDR", "Error: bw_r_rf16x32 read address is %b\n", rd_index_d1);
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//$error("RFRDADDR", "Error: bw_r_rf16x32 read address is %b\n", rd_index_d1);
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`endif
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end
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end
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else if (wrreq_d1 && (wr_index_d1 == 5'bX))
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else if (wrreq_d1 && (wr_index_d1 == 5'bX))
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begin
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begin
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 write address X"
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// 0in <fire -message "FATAL ERROR: bw_r_rf16x32 write address X"
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`ifdef DEFINE_0IN
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`else
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//$display("RFWRADDR", "Error: bw_r_rf16x32 write address is %b\n", wr_index_d1);
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//$error("RFWRADDR", "Error: bw_r_rf16x32 write address is %b\n", wr_index_d1);
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`endif
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end
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end
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end // always @ (...
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end // always @ (...
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// !`ifdef INNO_MUXEX
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`endif // !`ifdef INNO_MUXEX
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//reg [127:0] w0;
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//reg [127:0] w0;
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//reg [127:0] w1;
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//reg [127:0] w1;
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//reg [127:0] w2;
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//reg [127:0] w2;
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