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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_SCM
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`endif
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module bw_r_scm (/*AUTOARG*/
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module bw_r_scm (/*AUTOARG*/
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// Outputs
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// Outputs
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stb_rdata_ramc, stb_ld_full_raw, stb_ld_partial_raw,
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stb_rdata_ramc, stb_ld_full_raw, stb_ld_partial_raw,
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stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit,
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stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit,
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Line 126... |
wire [7:0] byte_match_mx ;
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wire [7:0] byte_match_mx ;
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wire [7:0] cam_hit ;
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wire [7:0] cam_hit ;
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wire [44:0] wdata_ramc ;
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wire [44:0] wdata_ramc ;
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wire [44:0] cam_data ;
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wire [44:0] cam_data ;
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wire [44:15] wr_data ;
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wire [44:15] wr_data ;
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`ifdef FPGA_SYN_SCM
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reg [4:0] stb_addr;
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reg [4:0] stb_addr;
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`endif
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integer i,j,k,l ;
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integer i,j,k,l ;
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begin
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begin
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cam_tid_tmp[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_tid_tmp[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_vld_tmp <= stb_cam_vld ;
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cam_vld_tmp <= stb_cam_vld ;
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end */
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end */
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`ifdef FPGA_SYN_SCM
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`else
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// Wordlines need to be generated locally
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always @ (posedge rclk)
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begin
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for (i=0;i<32;i=i+1)
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begin
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if ({stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]} == i)
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rw_wdline[i] <= 1'b1;
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else
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rw_wdline[i] <= 1'b0;
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end
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end
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`endif
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always @(posedge rclk)
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always @(posedge rclk)
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begin
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begin
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pipe_wr_data[44:15] <= stb_cam_data[44:15];
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pipe_wr_data[44:15] <= stb_cam_data[44:15];
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alt_wr_data[44:15] <= stb_alt_wr_data[44:15];
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alt_wr_data[44:15] <= stb_alt_wr_data[44:15];
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Line 177... |
rptr_vld_tmp <= stb_cam_rptr_vld ;
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rptr_vld_tmp <= stb_cam_rptr_vld ;
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cam_tid[1:0] <= stb_cam_cm_tid[1:0] ;
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cam_tid[1:0] <= stb_cam_cm_tid[1:0] ;
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//cam_tid[1:0] <= cam_tid_tmp[1:0] ;
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//cam_tid[1:0] <= cam_tid_tmp[1:0] ;
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//ldq <= stb_quad_ld_cam ; Bug 2870
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//ldq <= stb_quad_ld_cam ; Bug 2870
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alt_wsel <= stb_alt_wsel ;
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alt_wsel <= stb_alt_wsel ;
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`ifdef FPGA_SYN_SCM
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stb_addr <= {stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]};
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stb_addr <= {stb_cam_rw_tid[1:0],stb_cam_rw_ptr[2:0]};
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`endif
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end
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end
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assign ldq = stb_quad_ld_cam ;
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assign ldq = stb_quad_ld_cam ;
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assign rptr_vld = rptr_vld_tmp | rst_tri_en ;
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assign rptr_vld = rptr_vld_tmp | rst_tri_en ;
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assign wdata_ramc[44:0] = {wr_data[44:15],camwr_data[14:0]};
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assign wdata_ramc[44:0] = {wr_data[44:15],camwr_data[14:0]};
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// Write
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// Write
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always @ (negedge rclk)
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always @ (negedge rclk)
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begin
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begin
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`ifdef FPGA_SYN_SCM
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if(wptr_vld) begin
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if(wptr_vld) begin
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if(~rst_tri_en) begin
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if(~rst_tri_en) begin
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stb_ramc[stb_addr] <= wdata_ramc[44:0];
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stb_ramc[stb_addr] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end else begin
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end else begin
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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end
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end
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end
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end
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`else
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for (j=0;j<NUMENTRIES;j=j+1)
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begin
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if (rw_wdline[j] & wptr_vld)
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begin
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if (~rst_tri_en)
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begin
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stb_ramc[j] <= wdata_ramc[44:0];
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// write data is write-thru
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end
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else
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begin
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// INNO - default rd if wr squashed by scan_ena.
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stb_rdata_ramc[44:0] <= stb_ramc[j];
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end
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end
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end
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`endif
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// Read
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// Read
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`ifdef FPGA_SYN_SCM
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if(rptr_vld & ~scan_ena) begin
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if(rptr_vld & ~scan_ena) begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) begin
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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end
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end
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else begin
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else begin
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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stb_rdata_ramc[44:0] <= stb_ramc[stb_addr];
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end
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end
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end
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end
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`else
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for (k=0;k<NUMENTRIES;k=k+1)
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begin
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if (rw_wdline[k] & rptr_vld & ~scan_ena)
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begin
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if (rptr_vld & wptr_vld & ~rst_tri_en) // INNO - write-thru
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stb_rdata_ramc[44:0] <= wdata_ramc[44:0];
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else
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stb_rdata_ramc[44:0] <= stb_ramc[k];
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end
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end
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`endif
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end
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end
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//=========================================================================================
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//=========================================================================================
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// CAM contents of CAM RAM
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// CAM contents of CAM RAM
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//=========================================================================================
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//=========================================================================================
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