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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [cluster_header.v] - Diff between revs 105 and 113

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`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`	`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
`//`	`//`
`// ========== Copyright Header End ============================================`	`// ========== Copyright Header End ============================================`
`// The cluster header is instatiated as a hard macro.`	`// The cluster header is instatiated as a hard macro.`
`// This model is for simulation only.`	`// This model is for simulation only.`
`/*`	`include "sys.h"
`/* ========== Copyright Header Begin ==========================================`
`*`
`* OpenSPARC T1 Processor File: sys.h`
`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
`*`
`* The above named program is free software; you can redistribute it and/or`
`* modify it under the terms of the GNU General Public`
`* License version 2 as published by the Free Software Foundation.`
`*`
`* The above named program is distributed in the hope that it will be`
`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
`* General Public License for more details.`
`*`
`* You should have received a copy of the GNU General Public`
`* License along with this work; if not, write to the Free Software`
`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
`*`
`* ========== Copyright Header End ============================================`
`*/`
`// -- verilog --`
`////////////////////////////////////////////////////////////////////////`
`/*`
`//`
`// Description: Global header file that contain definitions that`
`// are common/shared at the systme level`
`*/`
`////////////////////////////////////////////////////////////////////////`
`//`
`// Setting the time scale`
`// If the timescale changes, JP_TIMESCALE may also have to change.`
`timescale 1ps/1ps

`//`
`// JBUS clock`
`// =========`
`//`



`// Afara Link Defines`
`// ==================`

`// Reliable Link`




`// Afara Link Objects`


`// Afara Link Object Format - Reliable Link`










`// Afara Link Object Format - Congestion`











`// Afara Link Object Format - Acknowledge`











`// Afara Link Object Format - Request`

















`// Afara Link Object Format - Message`



`// Acknowledge Types`




`// Request Types`





`// Afara Link Frame`



`//`
`// UCB Packet Type`
`// ===============`
`//`

















`//`
`// UCB Data Packet Format`
`// ======================`
`//`






























`// Size encoding for the UCB_SIZE_HI/LO field`
`// 000 - byte`
`// 001 - half-word`
`// 010 - word`
`// 011 - double-word`
`// 111 - quad-word`







`//`
`// UCB Interrupt Packet Format`
`// ===========================`
`//`










//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
//`define UCB_THR_LO 4 data packet format
//`define UCB_PKT_HI 3 // (4) packet type shared with
//`define UCB_PKT_LO 0 // data packet format







`//`
`// FCRAM Bus Widths`
`// ================`
`//`






`//`
`// ENET clock periods`
`// ==================`
`//`




`//`
`// JBus Bridge defines`
`// =================`
`//`











`//`
`// PCI Device Address Configuration`
`// ================================`
`//`
























`module cluster_header (/AUTOARG/`	`module cluster_header (/AUTOARG/`
`// Outputs`	`// Outputs`
`dbginit_l, cluster_grst_l, rclk, so,`	`dbginit_l, cluster_grst_l, rclk, so,`
`// Inputs`	`// Inputs`
Line 319...	Line 42...

`input si; // scan ports for reset flop repeaters`	`input si; // scan ports for reset flop repeaters`
`input se;`	`input se;`
`output so;`	`output so;`

	`ifdef FPGA_SYN
`// assign #10 rclk = gclk;`	`// assign #10 rclk = gclk;`
`// assign #10 dbginit_l = gdbginit_l;`	`// assign #10 dbginit_l = gdbginit_l;`
`// assign #10 cluster_grst_l = grst_l;`	`// assign #10 cluster_grst_l = grst_l;`
`// assign so = 1'b0;`	`// assign so = 1'b0;`

Line 335...	Line 58...
`always @(negedge rclk) begin`	`always @(negedge rclk) begin`
`dbginit_l <= gdbginit_l;`	`dbginit_l <= gdbginit_l;`
`cluster_grst_l <= grst_l;`	`cluster_grst_l <= grst_l;`
`end`	`end`

	`else

	`wire pre_sync_enable;`
	`wire sync_enable;`
	`wire cluster_grst_l;`
	`wire dbginit_l;`
	`wire rst_sync_so;`

	`bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up`
	`.so(),`
	`.q (pre_sync_enable),`
	`.ck (gclk),`
	`.d (cluster_cken),`
	`.sd(1'b0),`
	`.se(1'b0)`
	`);`


	`bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch`
	`.so (sync_enable),`
	`.ck (gclk),`
	`.sd (pre_sync_enable)`
	`);`

	`// NOTE! Pound delay in the below statement is meant to provide 10 ps`
	`// delay between gclk and rclk to allow the synchronizer for rst, dbginit,`
	`// and sync pulses to be modelled accurately. gclk and rclk need to have`
	`// at least one simulator timestep separation to allow the flop->flop`
	`// synchronizer to work correctly.`
	`assign #10 rclk = gclk & sync_enable;`

	`synchronizer_asr rst_repeater (`
	`.sync_out(cluster_grst_l),`
	`.so(rst_sync_so),`
	`.async_in(grst_l),`
	`.gclk(gclk),`
	`.rclk(rclk),`
	`.arst_l(arst_l),`
	`.si(si),`
	`.se(se)`
	`);`

	`synchronizer_asr dbginit_repeater (`
	`.sync_out(dbginit_l),`
	`.so(so),`
	`.async_in(gdbginit_l),`
	`.gclk(gclk),`
	`.rclk(rclk),`
	`.arst_l(adbginit_l),`
	`.si(rst_sync_so),`
	`.se(se)`
	`);`
	`endif






































`endmodule // cluster_header`	`endmodule // cluster_header`

`No newline at end of file`	`No newline at end of file`

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [cluster_header.v] - Diff between revs 105 and 113