OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_stb_ctl.v] - Diff between revs 105 and 113

Show entire file | Details | Blame | View Log

Rev 105 Rev 113
Line 16... Line 16... 
// You should have received a copy of the GNU General Public
 
// You should have received a copy of the GNU General Public
 
// License along with this work; if not, write to the Free Software
 
// License along with this work; if not, write to the Free Software
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
// 
// 
// ========== Copyright Header End ============================================
 
// ========== Copyright Header End ============================================
 
 
 
`ifdef SIMPLY_RISC_TWEAKS
 
 
 
`define SIMPLY_RISC_SCANIN .si(0)
 
 
 
`else
 
 
 
`define SIMPLY_RISC_SCANIN .si()
 
 
 
`endif
 
///////////////////////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////////////////////
 
/*
 
/*
 
//      Description:    Control for STB of LSU
 
//      Description:    Control for STB of LSU
 
//                              - Contains control for a single STB currently.
 
//                              - Contains control for a single STB currently.
 
*/
 
*/
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Global header file includes
 
// Global header file includes
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// system level definition file which contains the /*
 
`include        "sys.h" // system level definition file which contains the 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: sys.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
// -*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
// Description:         Global header file that contain definitions that
 
 
 
//                      are common/shared at the systme level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
//
 
 
 
// Setting the time scale
 
 
 
// If the timescale changes, JP_TIMESCALE may also have to change.
 
 
 
`timescale      1ps/1ps
 
 
 
 
 
 
 
//
 
 
 
// JBUS clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Defines
 
 
 
// ==================
 
 
 
 
 
 
 
// Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Objects
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Acknowledge Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Request Types
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Frame
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Packet Type
 
 
 
// ===============
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Data Packet Format
 
 
 
// ======================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 111 - quad-word
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// UCB Interrupt Packet Format
 
 
 
// ===========================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
 
 
 
//`define UCB_THR_LO             4             data packet format
 
 
 
//`define UCB_PKT_HI             3      // (4) packet type shared with
 
 
 
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// FCRAM Bus Widths
 
 
 
// ================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// ENET clock periods
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBus Bridge defines
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Device Address Configuration
 
 
 
// ================================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                                        // time scale definition
 
                                        // time scale definition
 
 
 
 
 
/*
 
`include "iop.h"
 
/* ========== Copyright Header Begin ==========================================
 
 
 
*
 
 
 
* OpenSPARC T1 Processor File: iop.h
 
 
 
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
 
 
 
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
 
 
 
*
 
 
 
* The above named program is free software; you can redistribute it and/or
 
 
 
* modify it under the terms of the GNU General Public
 
 
 
* License version 2 as published by the Free Software Foundation.
 
 
 
*
 
 
 
* The above named program is distributed in the hope that it will be
 
 
 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
 
 
 
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 
 
 
* General Public License for more details.
 
 
 
*
 
 
 
* You should have received a copy of the GNU General Public
 
 
 
* License along with this work; if not, write to the Free Software
 
 
 
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 
 
 
*
 
 
 
* ========== Copyright Header End ============================================
 
 
 
*/
 
 
 
//-*- verilog -*-
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
/*
 
 
 
//
 
 
 
//  Description:        Global header file that contain definitions that
 
 
 
//                      are common/shared at the IOP chip level
 
 
 
*/
 
 
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
 
 
 
 
// Address Map Defines
 
 
 
// ===================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CMP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
 
 
 
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// More IOP space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//Cache Crossbar Width and Field Defines
 
 
 
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
 
 
 
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
 
 
 
 
 
 
 
 
 
// Number of COS supported by EECU 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// 
 
 
// BSC bus sizes
 
 
 
// =============
 
 
 
//
 
 
 
 
 
 
 
// General
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CoS
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Bank
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
 
 
 
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
 
 
 
// Tag is: CTAG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC array sizes
 
 
 
//================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// BSC Port Definitions
 
 
 
// ====================
 
 
 
//
 
 
 
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
 
 
 
 
 
 
 
 
 
// Bits needed to represent above
 
 
 
 
 
 
 
 
 
 
 
// How wide the linked list pointers are
 
 
 
// 60b for no payload (2CoS)
 
 
 
// 80b for payload (2CoS)
 
 
 
 
 
 
 
//`define BSC_OBJ_PTR   80
 
 
 
//`define BSC_HD1_HI    69
 
 
 
//`define BSC_HD1_LO    60
 
 
 
//`define BSC_TL1_HI    59
 
 
 
//`define BSC_TL1_LO    50
 
 
 
//`define BSC_CT1_HI    49
 
 
 
//`define BSC_CT1_LO    40
 
 
 
//`define BSC_HD0_HI    29
 
 
 
//`define BSC_HD0_LO    20
 
 
 
//`define BSC_TL0_HI    19
 
 
 
//`define BSC_TL0_LO    10
 
 
 
//`define BSC_CT0_HI     9
 
 
 
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IOB defines
 
 
 
// ===========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
 
 
 
//`define IOB_INT_STAT_HI      31
 
 
 
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
 
 
 
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Bus Width
 
 
 
// ==================
 
 
 
//
 
 
 
//`define IOB_EECU_WIDTH       16  // ethernet egress command
 
 
 
//`define EECU_IOB_WIDTH       16
 
 
 
 
 
 
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
 
 
 
//`define NRAM_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
 
 
 
//`define ENET_ING_IOB_WIDTH    8
 
 
 
 
 
 
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
 
 
 
//`define ENET_EGR_IOB_WIDTH    4
 
 
 
 
 
 
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
 
 
 
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
 
 
 
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
 
 
 
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CIOP UCB Buf ID Type
 
 
 
// ====================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Interrupt Device ID
 
 
 
// ===================
 
 
 
//
 
 
 
// Caution: DUMMY_DEV_ID has to be 9 bit wide
 
 
 
//          for fields to line up properly in the IOB.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Soft Error related definitions 
 
 
// ==============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// CMP clock
 
 
 
// =========
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/IO Interface
 
 
 
// =================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// NRAM/ENET Interface
 
 
 
// ===================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// IO/FCRAM Interface
 
 
 
// ==================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// PCI Interface
 
 
 
// ==================
 
 
 
// Load/store size encodings
 
 
 
// -------------------------
 
 
 
// Size encoding
 
 
 
// 000 - byte
 
 
 
// 001 - half-word
 
 
 
// 010 - word
 
 
 
// 011 - double-word
 
 
 
// 100 - quad
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI<->SCTAG Interface
 
 
 
// =======================
 
 
 
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// JBI->IOB Mondo Header Format
 
 
 
// ============================
 
 
 
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
 
 
 
// ==============================
 
 
 
// Cycle  1 Header[15:8]
 
 
 
// Cycle  2 Header[ 7:0]
 
 
 
// Cycle  3 J_AD[127:120]
 
 
 
// Cycle  4 J_AD[119:112]
 
 
 
// .....
 
 
 
// Cycle 18 J_AD[  7:  0]
 
 
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
// Local header file includes / local defines
 
// Local header file includes / local defines
 
////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////
 
 
 
 
 
module lsu_stb_ctl (/*AUTOARG*/
 
module lsu_stb_ctl (/*AUTOARG*/
Line 1346... Line 236... 
   wire       rst_l;
 
   wire       rst_l;
 
   wire       stb_ctl_rst_l;
 
   wire       stb_ctl_rst_l;
 
 
 
 
 
   dffrl_async rstff(.din (grst_l),
 
   dffrl_async rstff(.din (grst_l),
 
                     .q   (stb_ctl_rst_l),
 
                     .q   (stb_ctl_rst_l),
 
                     .clk (clk), .se(se), .si(), .so(),
 
                     .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
 
                     .rst_l (arst_l));
 
                     .rst_l (arst_l));
 
   assign     rst_l = stb_ctl_rst_l;
 
   assign     rst_l = stb_ctl_rst_l;
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      RESET
 
//      RESET
Line 1381... Line 271... 
 
 
 
 
// This vector is one-hot. Assumption is that stb is a circular queue.
 
// This vector is one-hot. Assumption is that stb is a circular queue.
 
// deadlock has to be broken between oldest and youngest entry when the
 
// deadlock has to be broken between oldest and youngest entry when the
 
// queue is full. The dfq ptr is used to mark oldest
 
// queue is full. The dfq ptr is used to mark oldest
 
 
 
 
 
dff #(2)  rq_stgd1       (
 
dff_s #(2)  rq_stgd1       (
 
        .din    ({pcx_rq_for_stb_d1,pcx_req_squash}),
 
        .din    ({pcx_rq_for_stb_d1,pcx_req_squash}),
 
        .q      ({pcx_rq_for_stb_d2,pcx_req_squash_d2}),
 
        .q      ({pcx_rq_for_stb_d2,pcx_req_squash_d2}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
wire    ffu_bst_wr_g ;
 
wire    ffu_bst_wr_g ;
 
dff #(1)  ff_bstg       (
 
dff_s #(1)  ff_bstg       (
 
        .din    (lsu_blk_st_m),
 
        .din    (lsu_blk_st_m),
 
        .q      (ffu_bst_wr_g),
 
        .q      (ffu_bst_wr_g),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
wire    full_flush_st_g ;
 
wire    full_flush_st_g ;
 
// flush_pipe does not apply to blk st wr.
 
// flush_pipe does not apply to blk st wr.
 
assign  full_flush_st_g = (stb_flush_st_g | (lsu_stbctl_flush_pipe_w & ~ffu_bst_wr_g)) & stb_cam_wvld_g ;
 
assign  full_flush_st_g = (stb_flush_st_g | (lsu_stbctl_flush_pipe_w & ~ffu_bst_wr_g)) & stb_cam_wvld_g ;
Line 1405... Line 295... 
// timing fix: 5/6 -  begin
 
// timing fix: 5/6 -  begin
 
// qual dec_rptr_pcx w/ tlb camhit and in qctl1 move kill qual after store pick
 
// qual dec_rptr_pcx w/ tlb camhit and in qctl1 move kill qual after store pick
 
wire      tlb_cam_hit_g, tlb_hit_g;
 
wire      tlb_cam_hit_g, tlb_hit_g;
 
wire      dtlb_bypass_m, dtlb_bypass_g ;
 
wire      dtlb_bypass_m, dtlb_bypass_g ;
 
 
 
 
 
dff #(1)  ff_dtlb_bypass_m       (
 
dff_s #(1)  ff_dtlb_bypass_m       (
 
        .din    (lsu_dtlb_bypass_e),
 
        .din    (lsu_dtlb_bypass_e),
 
        .q      (dtlb_bypass_m),
 
        .q      (dtlb_bypass_m),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
dff #(1)  ff_dtlb_bypass_g       (
 
dff_s #(1)  ff_dtlb_bypass_g       (
 
        .din    (dtlb_bypass_m),
 
        .din    (dtlb_bypass_m),
 
        .q      (dtlb_bypass_g),
 
        .q      (dtlb_bypass_g),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
dff #(1)  ff_tlb_cam_hit_g       (
 
dff_s #(1)  ff_tlb_cam_hit_g       (
 
        .din    (tlb_cam_hit),
 
        .din    (tlb_cam_hit),
 
        .q      (tlb_cam_hit_g),
 
        .q      (tlb_cam_hit_g),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
assign  tlb_hit_g  =  tlb_cam_hit_g | dtlb_bypass_g | ffu_bst_wr_g; //bug6406/eco6610
 
assign  tlb_hit_g  =  tlb_cam_hit_g | dtlb_bypass_g | ffu_bst_wr_g; //bug6406/eco6610
 
// timing fix: 5/6 -  end
 
// timing fix: 5/6 -  end
 
 
 
 
Line 1466... Line 356... 
wire  rmo_st_satuated;
 
wire  rmo_st_satuated;
 
//dff #(1) rmo_st_satuated_ff  (
 
//dff #(1) rmo_st_satuated_ff  (
 
//    .din (lsu_outstanding_rmo_st_max),
 
//    .din (lsu_outstanding_rmo_st_max),
 
//    .q   (rmo_st_satuated),
 
//    .q   (rmo_st_satuated),
 
//    .clk    (clk),
 
//    .clk    (clk),
 
//    .se     (se), .si     (), .so ()
 
//    .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
//);
 
//);
 
 
 
 
 
   assign rmo_st_satuated  =  lsu_outstanding_rmo_st_max;
 
   assign rmo_st_satuated  =  lsu_outstanding_rmo_st_max;
 
 
 
 
 
wire    [7:0]    stb_state_ced_spec ;
 
wire    [7:0]    stb_state_ced_spec ;
Line 1508... Line 398... 
assign  st_vld_squash_g = any_inflight_iss_g & full_flush_st_g ;
 
assign  st_vld_squash_g = any_inflight_iss_g & full_flush_st_g ;
 
//assign        st_vld_squash_g = (|inflight_vld_g[7:0]) & full_flush_st_g ;
 
//assign        st_vld_squash_g = (|inflight_vld_g[7:0]) & full_flush_st_g ;
 
 
 
 
 
wire st_pcx_rq_kill_tmp,st_vld_squash_tmp ;
 
wire st_pcx_rq_kill_tmp,st_vld_squash_tmp ;
 
wire st_dtlb_perr_w2 ;
 
wire st_dtlb_perr_w2 ;
 
dff #(5)  stkill_stgd1       (
 
dff_s #(5)  stkill_stgd1       (
 
        .din    ({st_pcx_rq_kill_g,st_vld_squash_g,
 
        .din    ({st_pcx_rq_kill_g,st_vld_squash_g,
 
                any_inflight_iss_g,pick_inflight_iss_g,st_dtlb_perr_g}),
 
                any_inflight_iss_g,pick_inflight_iss_g,st_dtlb_perr_g}),
 
        .q      ({st_pcx_rq_kill_tmp,st_vld_squash_tmp,
 
        .q      ({st_pcx_rq_kill_tmp,st_vld_squash_tmp,
 
                any_inflight_iss_w2,pick_inflight_iss_w2,st_dtlb_perr_w2}),
 
                any_inflight_iss_w2,pick_inflight_iss_w2,st_dtlb_perr_w2}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
assign  st_pcx_rq_kill_w2 =
 
assign  st_pcx_rq_kill_w2 =
 
                st_pcx_rq_kill_tmp |
 
                st_pcx_rq_kill_tmp |
 
                (pick_inflight_iss_w2 & st_dtlb_perr_w2);
 
                (pick_inflight_iss_w2 & st_dtlb_perr_w2);
Line 1563... Line 453... 
assign  stb_rptr_dfq_new[3:0]    =       stb_rptr_dfq[3:0]  + {3'b0, incr_dfq_ptr} ;
 
assign  stb_rptr_dfq_new[3:0]    =       stb_rptr_dfq[3:0]  + {3'b0, incr_dfq_ptr} ;
 
//assign        stb_rptr_dfq_new[3:0]   =       stb_rptr_dfq[3:0]  + {3'b0, st_ack_dq_stb} ;
 
//assign        stb_rptr_dfq_new[3:0]   =       stb_rptr_dfq[3:0]  + {3'b0, st_ack_dq_stb} ;
 
 
 
 
 
assign stb_rptr_dfq_en = st_ack_dq_stb | incr_dfq_ptr ;
 
assign stb_rptr_dfq_en = st_ack_dq_stb | incr_dfq_ptr ;
 
 
 
 
 
dffre #(4)  rptr_d      (
 
dffre_s #(4)  rptr_d    (
 
        .din            (stb_rptr_dfq_new[3:0]),.q       (stb_rptr_dfq[3:0]),
 
        .din            (stb_rptr_dfq_new[3:0]),.q       (stb_rptr_dfq[3:0]),
 
        .en             (stb_rptr_dfq_en),      .rst    (reset),
 
        .en             (stb_rptr_dfq_en),      .rst    (reset),
 
        .clk            (clk),
 
        .clk            (clk),
 
        .se             (se),   .si     (), .so ()
 
        .se             (se),   `SIMPLY_RISC_SCANIN, .so        ()
 
        );
 
        );
 
 
 
 
 
//assign        stb_dfq_rptr[2:0] = stb_rptr_dfq_new[2:0] ;
 
//assign        stb_dfq_rptr[2:0] = stb_rptr_dfq_new[2:0] ;
 
 
 
 
 
// Decode Read Ptr
 
// Decode Read Ptr
Line 1584... Line 474... 
assign  dec_rptr_dfq[5] =  stb_rptr_dfq[2] & ~stb_rptr_dfq[1] &  stb_rptr_dfq[0] ;
 
assign  dec_rptr_dfq[5] =  stb_rptr_dfq[2] & ~stb_rptr_dfq[1] &  stb_rptr_dfq[0] ;
 
assign  dec_rptr_dfq[6] =  stb_rptr_dfq[2] &  stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
 
assign  dec_rptr_dfq[6] =  stb_rptr_dfq[2] &  stb_rptr_dfq[1] & ~stb_rptr_dfq[0] ;
 
assign  dec_rptr_dfq[7] =  stb_rptr_dfq[2] &  stb_rptr_dfq[1] &  stb_rptr_dfq[0] ;
 
assign  dec_rptr_dfq[7] =  stb_rptr_dfq[2] &  stb_rptr_dfq[1] &  stb_rptr_dfq[0] ;
 
 
 
 
 
// Stge dfq ptr and dq vld by 2-cycles to appropriate invalidation pt
 
// Stge dfq ptr and dq vld by 2-cycles to appropriate invalidation pt
 
dff #(9)  dq_stgd1       (
 
dff_s #(9)  dq_stgd1       (
 
        .din    ({dec_rptr_dfq[7:0],st_ack_dq_stb}),
 
        .din    ({dec_rptr_dfq[7:0],st_ack_dq_stb}),
 
        .q      ({dqptr_d1[7:0],dq_vld_d1}),
 
        .q      ({dqptr_d1[7:0],dq_vld_d1}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
dff #(9)  dq_stgd2       (
 
dff_s #(9)  dq_stgd2       (
 
        .din    ({dqptr_d1[7:0],dq_vld_d1}),
 
        .din    ({dqptr_d1[7:0],dq_vld_d1}),
 
        .q      ({dqptr_d2[7:0],dq_vld_d2}),
 
        .q      ({dqptr_d2[7:0],dq_vld_d2}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      WPTR FOR STB
 
//      WPTR FOR STB
 
//=========================================================================================
 
//=========================================================================================
Line 1616... Line 506... 
 
 
 
 
assign  stb_wptr_new[3:0]       =       (full_flush_st_g | st_dtlb_perr_g) ?
 
assign  stb_wptr_new[3:0]       =       (full_flush_st_g | st_dtlb_perr_g) ?
 
                                                        stb_wptr_prev[3:0] :
 
                                                        stb_wptr_prev[3:0] :
 
                                                        stb_wptr[3:0] + {3'b0, stb_cam_wvld_m} ;
 
                                                        stb_wptr[3:0] + {3'b0, stb_cam_wvld_m} ;
 
 
 
 
 
dff  wvld_stgg       (
 
dff_s  wvld_stgg       (
 
        .din    (stb_cam_wvld_m), .q      (stb_cam_wvld_g),
 
        .din    (stb_cam_wvld_m), .q      (stb_cam_wvld_g),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
//assign        stb_wvld_g = stb_cam_wvld_g & ~full_flush_st_g ;
 
//assign        stb_wvld_g = stb_cam_wvld_g & ~full_flush_st_g ;
 
 
 
 
 
dffre #(4)  wptr_new    (
 
dffre_s #(4)  wptr_new    (
 
        .din            (stb_wptr_new[3:0]),    .q      (stb_wptr[3:0]),
 
        .din            (stb_wptr_new[3:0]),    .q      (stb_wptr[3:0]),
 
        .en             (update_stb_wptr),    .rst    (reset),
 
        .en             (update_stb_wptr),    .rst    (reset),
 
        .clk            (clk),
 
        .clk            (clk),
 
        .se             (se), .si     (), .so ()
 
        .se             (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
assign  stb_wrptr[2:0]   = stb_wptr[2:0] ;
 
assign  stb_wrptr[2:0]   = stb_wptr[2:0] ;
 
 
 
 
 
wire [2:0] stb_wptr_m ;
 
wire [2:0] stb_wptr_m ;
Line 1652... Line 542... 
assign  dec_wptr_m[4] =  stb_wptr_m[2] & ~stb_wptr_m[1] & ~stb_wptr_m[0] ;
 
assign  dec_wptr_m[4] =  stb_wptr_m[2] & ~stb_wptr_m[1] & ~stb_wptr_m[0] ;
 
assign  dec_wptr_m[5] =  stb_wptr_m[2] & ~stb_wptr_m[1] &  stb_wptr_m[0] ;
 
assign  dec_wptr_m[5] =  stb_wptr_m[2] & ~stb_wptr_m[1] &  stb_wptr_m[0] ;
 
assign  dec_wptr_m[6] =  stb_wptr_m[2] &  stb_wptr_m[1] & ~stb_wptr_m[0] ;
 
assign  dec_wptr_m[6] =  stb_wptr_m[2] &  stb_wptr_m[1] & ~stb_wptr_m[0] ;
 
assign  dec_wptr_m[7] =  stb_wptr_m[2] &  stb_wptr_m[1] &  stb_wptr_m[0] ;
 
assign  dec_wptr_m[7] =  stb_wptr_m[2] &  stb_wptr_m[1] &  stb_wptr_m[0] ;
 
 
 
 
 
dff #(8)  dwptr_stgg       (
 
dff_s #(8)  dwptr_stgg       (
 
        .din    (dec_wptr_m[7:0]), .q      (dec_wptr_g[7:0]),
 
        .din    (dec_wptr_m[7:0]), .q      (dec_wptr_g[7:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
// stb_wptr_prev represents the latest valid entry in stb
 
// stb_wptr_prev represents the latest valid entry in stb
 
/*dffre #(4)  wptr_prev   (
 
/*dffre #(4)  wptr_prev   (
 
        .din            (stb_wptr[3:0]),        .q      (stb_wptr_prev[3:0]),
 
        .din            (stb_wptr[3:0]),        .q      (stb_wptr_prev[3:0]),
 
        .en             (update_stb_wptr),      .rst    (reset),
 
        .en             (update_stb_wptr),      .rst    (reset),
 
        .clk            (clk),
 
        .clk            (clk),
 
        .se             (se), .si     (), .so ()
 
        .se             (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );*/
 
        );*/
 
 
 
 
 
assign  stb_wptr_prev[3:0] = stb_wptr[3:0] - {4'b0001} ;
 
assign  stb_wptr_prev[3:0] = stb_wptr[3:0] - {4'b0001} ;
 
 
 
 
 
// Bug 2419 - In case this is a critical path, a flop can be inserted.
 
// Bug 2419 - In case this is a critical path, a flop can be inserted.
Line 1678... Line 568... 
//=========================================================================================
 
//=========================================================================================
 
 
 
 
 
wire    [3:0]    stb_wptr_w2 ;
 
wire    [3:0]    stb_wptr_w2 ;
 
 
 
 
 
// Count should not include stores in pipe-stages 'g' or before.
 
// Count should not include stores in pipe-stages 'g' or before.
 
dff #(4)  wptr_stgw2       (
 
dff_s #(4)  wptr_stgw2       (
 
        .din    (stb_wptr[3:0]), .q      (stb_wptr_w2[3:0]),
 
        .din    (stb_wptr[3:0]), .q      (stb_wptr_w2[3:0]),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
assign  lsu_stbcnt[3:0] =  (stb_wptr_w2[3:0] - stb_rptr_dfq[3:0]) ;
 
assign  lsu_stbcnt[3:0] =  (stb_wptr_w2[3:0] - stb_rptr_dfq[3:0]) ;
 
 
 
 
 
// Performance Cntr Info
 
// Performance Cntr Info
 
wire    stb_full_w2 ;
 
wire    stb_full_w2 ;
 
assign  stb_full_w2 = lsu_stbcnt[2] & lsu_stbcnt[1] & lsu_stbcnt[0] ;
 
assign  stb_full_w2 = lsu_stbcnt[2] & lsu_stbcnt[1] & lsu_stbcnt[0] ;
 
dff   sfull (
 
dff_s   sfull (
 
        .din    (stb_full_w2), .q      (stb_full),
 
        .din    (stb_full_w2), .q      (stb_full),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
//=========================================================================================
 
//=========================================================================================
 
//      CONTROL STATE
 
//      CONTROL STATE
 
//=========================================================================================
 
//=========================================================================================
Line 1718... Line 608... 
//
 
//
 
// Total - 14b.
 
// Total - 14b.
 
 
 
 
 
// ack_id is internally tracked. 
// ack_id is internally tracked. 
// There can only be one outstanding
 
// There can only be one outstanding
 
dffre #(8)  ackptr_ff   (
 
dffre_s #(8)  ackptr_ff (
 
        .din            (dec_rptr_pcx[7:0]), .q  (dec_ackptr[7:0]),
 
        .din            (dec_rptr_pcx[7:0]), .q  (dec_ackptr[7:0]),
 
        .en             (pcx_rq_for_stb), .rst (reset),
 
        .en             (pcx_rq_for_stb), .rst (reset),
 
        .clk            (clk),
 
        .clk            (clk),
 
        .se             (se),   .si     (), .so ()
 
        .se             (se),   `SIMPLY_RISC_SCANIN, .so        ()
 
        );
 
        );
 
 
 
 
 
 
 
 
 
assign  ack_vld = cpx_st_ack_tid ;
 
assign  ack_vld = cpx_st_ack_tid ;
 
//assign        st_dc_hit_g = lsu_st_hit_g ;
 
//assign        st_dc_hit_g = lsu_st_hit_g ;
Line 1750... Line 640... 
//      tlb_pgnum_m[39]  & ~(~tlb_pgnum_m[38]  & tlb_pgnum_m[37])  & ~flsh_inst_m;
 
//      tlb_pgnum_m[39]  & ~(~tlb_pgnum_m[38]  & tlb_pgnum_m[37])  & ~flsh_inst_m;
 
 
 
 
 
wire   [2:0]  stb_alt_addr_g;
 
wire   [2:0]  stb_alt_addr_g;
 
wire          stb_alt_sel_g;
 
wire          stb_alt_sel_g;
 
 
 
 
 
dff #(4) ff_alt_addr_g       (
 
dff_s #(4) ff_alt_addr_g       (
 
        .din    ({stb_alt_sel,stb_alt_addr[2:0]}),
 
        .din    ({stb_alt_sel,stb_alt_addr[2:0]}),
 
        .q      ({stb_alt_sel_g,stb_alt_addr_g[2:0]}),
 
        .q      ({stb_alt_sel_g,stb_alt_addr_g[2:0]}),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
wire  flsh_inst_g;
 
wire  flsh_inst_g;
 
dff #(1) ff_flsh_inst_g       (
 
dff_s #(1) ff_flsh_inst_g       (
 
        .din    (flsh_inst_m),
 
        .din    (flsh_inst_m),
 
        .q      (flsh_inst_g),
 
        .q      (flsh_inst_g),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
wire   stb_alt_io_g , tlb_pgnum_io_g ;
 
wire   stb_alt_io_g , tlb_pgnum_io_g ;
 
 
 
 
 
assign  stb_alt_io_g  =
 
assign  stb_alt_io_g  =
Line 1831... Line 721... 
     stb_state_vld[7] ? stb_state_io[7] :
 
     stb_state_vld[7] ? stb_state_io[7] :
 
        stb_alt_sel_g ? stb_alt_io_g :
 
        stb_alt_sel_g ? stb_alt_io_g :
 
                        tlb_pgnum_io_g ;
 
                        tlb_pgnum_io_g ;
 
 
 
 
 
 
 
 
 
dff  rqsel_stgg       (
 
dff_s  rqsel_stgg       (
 
        .din    (pcx_rq_for_stb), .q      (pcx_rq_for_stb_d1),
 
        .din    (pcx_rq_for_stb), .q      (pcx_rq_for_stb_d1),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si     (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
// Use of tlb_pgnum_m will be critical !!! 
// Use of tlb_pgnum_m will be critical !!! 
 
 
 
 
//always @( posedge clk)
 
//always @( posedge clk)
Line 1921... Line 811... 
   assign rmo_pend = |rmo_pend_ackptr[7:0];
 
   assign rmo_pend = |rmo_pend_ackptr[7:0];
 
 
 
 
 
   wire   rmo_pend_rst;
 
   wire   rmo_pend_rst;
 
   assign rmo_pend_rst  =  reset | stb_dq_rmo;
 
   assign rmo_pend_rst  =  reset | stb_dq_rmo;
 
 
 
 
 
   dffre #(1)  ff_rmo_pend      (
 
   dffre_s #(1)  ff_rmo_pend      (
 
         .din  (rmo_pend),
 
         .din  (rmo_pend),
 
         .q    (rmo_pend_d1),
 
         .q    (rmo_pend_d1),
 
         .en   (st_vld_rq_d2),
 
         .en   (st_vld_rq_d2),
 
         .rst  (rmo_pend_rst),
 
         .rst  (rmo_pend_rst),
 
         .clk  (clk),
 
         .clk  (clk),
 
         .se   (se), .si     (), .so ()
 
         .se   (se), `SIMPLY_RISC_SCANIN, .so ()
 
         );
 
         );
 
 
 
 
 
   // ok to use either dec_ackptr[7:0] OR dec_rptr_dfq[7:0] 'cos the stores younger to 1st RMO store
 
   // ok to use either dec_ackptr[7:0] OR dec_rptr_dfq[7:0] 'cos the stores younger to 1st RMO store
 
   // are not issued ('cos vld of RMO store is not reset). Hence ackptr and rptr_dfq will be the same
 
   // are not issued ('cos vld of RMO store is not reset). Hence ackptr and rptr_dfq will be the same
 
   // when rmo_pend=0.
 
   // when rmo_pend=0.
Line 2005... Line 895... 
   //assign stb_state_vld_set[7:0] = dec_wptr_g[7:0] & {8{stb_wvld_g & thrd_en_g}} ;
 
   //assign stb_state_vld_set[7:0] = dec_wptr_g[7:0] & {8{stb_wvld_g & thrd_en_g}} ;
 
   assign stb_state_vld_din[7:0] = stb_state_vld_set[7:0] |
 
   assign stb_state_vld_din[7:0] = stb_state_vld_set[7:0] |
 
                                  (~stb_state_rst[7:0] & stb_state_vld[7:0]);
 
                                  (~stb_state_rst[7:0] & stb_state_vld[7:0]);
 
 
 
 
 
   wire [7:0] stb_state_vld_tmp ;
 
   wire [7:0] stb_state_vld_tmp ;
 
   dff #(8)  ff_stb_state_vld       (
 
   dff_s #(8)  ff_stb_state_vld       (
 
        .din    (stb_state_vld_din[7:0]),
 
        .din    (stb_state_vld_din[7:0]),
 
        .q      (stb_state_vld_tmp[7:0]    ),
 
        .q      (stb_state_vld_tmp[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
   assign stb_state_vld[7:0] = stb_state_vld_tmp[7:0] & ~flush_vld_w2[7:0] ;
 
   assign stb_state_vld[7:0] = stb_state_vld_tmp[7:0] & ~flush_vld_w2[7:0] ;
 
 
 
 
 
   wire [7:0] stb_state_vld_set_w2 ;
 
   wire [7:0] stb_state_vld_set_w2 ;
 
   dff #(8)  ff_stb_state_vld_set       (
 
   dff_s #(8)  ff_stb_state_vld_set       (
 
        .din    (stb_state_vld_set[7:0]),
 
        .din    (stb_state_vld_set[7:0]),
 
        .q      (stb_state_vld_set_w2[7:0]    ),
 
        .q      (stb_state_vld_set_w2[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
   assign flush_vld_w2[7:0] = stb_state_vld_set_w2[7:0] & {8{st_vld_squash_w2}} ;
 
   assign flush_vld_w2[7:0] = stb_state_vld_set_w2[7:0] & {8{st_vld_squash_w2}} ;
 
 
 
 
 
   // The stb valids for the scm need not include the intermediate flush condition
 
   // The stb valids for the scm need not include the intermediate flush condition
Line 2032... Line 922... 
   // Bug 3201 - rmo st are made invisible to loads.
 
   // Bug 3201 - rmo st are made invisible to loads.
 
 
 
 
 
   wire [7:0]  st_scm_vld ;
 
   wire [7:0]  st_scm_vld ;
 
   assign st_scm_vld[7:0] = stb_state_vld_din[7:0] & ~stb_state_rmo[7:0] ;
 
   assign st_scm_vld[7:0] = stb_state_vld_din[7:0] & ~stb_state_rmo[7:0] ;
 
 
 
 
 
   dff #(8)  ff_st_scm_vld       (
 
   dff_s #(8)  ff_st_scm_vld       (
 
        .din    (st_scm_vld[7:0]),
 
        .din    (st_scm_vld[7:0]),
 
        .q      (stb_state_vld_out[7:0]    ),
 
        .q      (stb_state_vld_out[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
   //ced
 
   //ced
 
   assign stb_state_ced_set[7:0] = dec_ackptr[7:0] & {8{st_vld_rq_d2}} ;
 
   assign stb_state_ced_set[7:0] = dec_ackptr[7:0] & {8{st_vld_rq_d2}} ;
 
   // Timing fix.
 
   // Timing fix.
Line 2049... Line 939... 
   assign stb_state_ced_din[7:0] = ~stb_state_rst[7:0] &
 
   assign stb_state_ced_din[7:0] = ~stb_state_rst[7:0] &
 
                                        (stb_state_ced_set[7:0] | stb_state_ced[7:0]);
 
                                        (stb_state_ced_set[7:0] | stb_state_ced[7:0]);
 
   //assign stb_state_ced_din[7:0] = stb_state_ced_set[7:0] | 
   //assign stb_state_ced_din[7:0] = stb_state_ced_set[7:0] | 
   //                               (~stb_state_rst[7:0] & stb_state_ced[7:0]);
 
   //                               (~stb_state_rst[7:0] & stb_state_ced[7:0]);
 
 
 
 
 
   dff #(8)  ff_stb_state_ced       (
 
   dff_s #(8)  ff_stb_state_ced       (
 
        .din    (stb_state_ced_din[7:0]),
 
        .din    (stb_state_ced_din[7:0]),
 
        .q      (stb_state_ced[7:0]    ),
 
        .q      (stb_state_ced[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
   //ack
 
   //ack
 
   assign stb_state_ack_set[7:0] = dec_ackptr[7:0] & {8{ack_vld}};
 
   assign stb_state_ack_set[7:0] = dec_ackptr[7:0] & {8{ack_vld}};
 
   assign stb_state_ack_din[7:0] = stb_state_ack_set[7:0] |
 
   assign stb_state_ack_din[7:0] = stb_state_ack_set[7:0] |
 
                                  (~stb_state_rst[7:0] & stb_state_ack[7:0]);
 
                                  (~stb_state_rst[7:0] & stb_state_ack[7:0]);
 
 
 
 
 
   dff #(8)  ff_stb_state_ack       (
 
   dff_s #(8)  ff_stb_state_ack       (
 
        .din    (stb_state_ack_din[7:0]),
 
        .din    (stb_state_ack_din[7:0]),
 
        .q      (stb_state_ack[7:0]    ),
 
        .q      (stb_state_ack[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
   //spec. write
 
   //spec. write
 
   wire [7:0] spec_wrt;
 
   wire [7:0] spec_wrt;
 
   assign     spec_wrt [7:0] = dec_wptr_m[7:0] & {8{stb_cam_wvld_m}};
 
   assign     spec_wrt [7:0] = dec_wptr_m[7:0] & {8{stb_cam_wvld_m}};
Line 2081... Line 971... 
  // moved state_io logic from ctldp 
  // moved state_io logic from ctldp 
 
 
 
 
  assign stb_state_io_din[7:0]  =  (stb_state_vld_set[7:0] & {8{stb_non_l2bnk_g}}) |
 
  assign stb_state_io_din[7:0]  =  (stb_state_vld_set[7:0] & {8{stb_non_l2bnk_g}}) |
 
                                   (~stb_state_rst[7:0] & stb_state_io[7:0]);
 
                                   (~stb_state_rst[7:0] & stb_state_io[7:0]);
 
 
 
 
 
   dff #(8)  ff_stb_state_io       (
 
   dff_s #(8)  ff_stb_state_io       (
 
        .din    (stb_state_io_din[7:0]),
 
        .din    (stb_state_io_din[7:0]),
 
        .q      (stb_state_io[7:0]    ),
 
        .q      (stb_state_io[7:0]    ),
 
        .clk    (clk),
 
        .clk    (clk),
 
        .se     (se), .si (), .so ()
 
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
 
        );
 
        );
 
 
 
 
 
// always->dff translation end    
// always->dff translation end    
// streaming unit does not have to care about outstanding rmo sparc-stores.
 
// streaming unit does not have to care about outstanding rmo sparc-stores.
 
// membar will take care of that. spu must insert appr. delay in sampling signal.
 
// membar will take care of that. spu must insert appr. delay in sampling signal.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.