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Line 16... |
// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/*
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/*
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// Module Name: sparc_exu_ecc
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// Module Name: sparc_exu_ecc
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// Description: This block performs the ecc check and correction as well as
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// Description: This block performs the ecc check and correction as well as
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// doing the w2 write port arbitration and the w2 ecc generation.
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// doing the w2 write port arbitration and the w2 ecc generation.
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Line 92... |
wire [63:0] exu_lsu_rs3_data_m;
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wire [63:0] exu_lsu_rs3_data_m;
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wire [63:0] error_data_m;
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wire [63:0] error_data_m;
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assign clk = rclk;
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assign clk = rclk;
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// Pass along ecc parity bits from RF
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// Pass along ecc parity bits from RF
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dff #(8) rs1_ecc_d2e(.din(byp_ecc_rs1_synd_d[7:0]), .clk(clk), .q(rs1_ecc_e[7:0]),
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dff_s #(8) rs1_ecc_d2e(.din(byp_ecc_rs1_synd_d[7:0]), .clk(clk), .q(rs1_ecc_e[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(8) rs2_ecc_d2e(.din(byp_ecc_rs2_synd_d[7:0]), .clk(clk), .q(rs2_ecc_e[7:0]),
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dff_s #(8) rs2_ecc_d2e(.din(byp_ecc_rs2_synd_d[7:0]), .clk(clk), .q(rs2_ecc_e[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(8) rs3_ecc_d2e(.din(byp_ecc_rs3_synd_d[7:0]), .clk(clk), .q(rs3_ecc_e[7:0]),
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dff_s #(8) rs3_ecc_d2e(.din(byp_ecc_rs3_synd_d[7:0]), .clk(clk), .q(rs3_ecc_e[7:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// Check the ecc for all 4 outputs from RF
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// Check the ecc for all 4 outputs from RF
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zzecc_exu_chkecc2 chk_rs1(.d(byp_ecc_rcc_data_e[63:0]),
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zzecc_exu_chkecc2 chk_rs1(.d(byp_ecc_rcc_data_e[63:0]),
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.vld(ecl_ecc_rs1_use_rf_e),
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.vld(ecl_ecc_rs1_use_rf_e),
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.p(rs1_ecc_e[7:0]),
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.p(rs1_ecc_e[7:0]),
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Line 117... |
.p(rs3_ecc_e[7:0]),
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.p(rs3_ecc_e[7:0]),
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.q(rs3_err_e[6:0]),
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.q(rs3_err_e[6:0]),
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.ce(ecc_ecl_rs3_ce), .ue(ecc_ecl_rs3_ue), .ne());
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.ce(ecc_ecl_rs3_ce), .ue(ecc_ecl_rs3_ue), .ne());
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// Put results from checkers into flops
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// Put results from checkers into flops
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dff #(7) rs1_err_e2m(.din(rs1_err_e[6:0]), .clk(clk), .q(rs1_err_m[6:0]),
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dff_s #(7) rs1_err_e2m(.din(rs1_err_e[6:0]), .clk(clk), .q(rs1_err_m[6:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(7) rs2_err_e2m(.din(rs2_err_e[6:0]), .clk(clk), .q(rs2_err_m[6:0]),
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dff_s #(7) rs2_err_e2m(.din(rs2_err_e[6:0]), .clk(clk), .q(rs2_err_m[6:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(7) rs3o_err_e2m(.din(rs3_err_e[6:0]), .clk(clk), .q(rs3_err_m[6:0]),
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dff_s #(7) rs3o_err_e2m(.din(rs3_err_e[6:0]), .clk(clk), .q(rs3_err_m[6:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// Pass along RF data to M stage
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// Pass along RF data to M stage
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dff #(64) rs1_data_e2m(.din(byp_ecc_rcc_data_e[63:0]), .clk(clk), .q(byp_ecc_rcc_data_m[63:0]),
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dff_s #(64) rs1_data_e2m(.din(byp_ecc_rcc_data_e[63:0]), .clk(clk), .q(byp_ecc_rcc_data_m[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(64) rs2_data_e2m(.din(byp_alu_rs2_data_e[63:0]), .clk(clk), .q(byp_alu_rs2_data_m[63:0]),
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dff_s #(64) rs2_data_e2m(.din(byp_alu_rs2_data_e[63:0]), .clk(clk), .q(byp_alu_rs2_data_m[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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dff #(64) rs3_data_e2m(.din(byp_ecc_rs3_data_e[63:0]), .clk(clk),
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dff_s #(64) rs3_data_e2m(.din(byp_ecc_rs3_data_e[63:0]), .clk(clk),
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.q(exu_lsu_rs3_data_m[63:0]),
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.q(exu_lsu_rs3_data_m[63:0]),
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.se(se), .si(), .so());
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.se(se), `SIMPLY_RISC_SCANIN, .so());
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// Mux between 3 different ports for syndrome and data
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// Mux between 3 different ports for syndrome and data
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assign sel_rs1_m = ~ecl_ecc_sel_rs1_m_l;
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assign sel_rs1_m = ~ecl_ecc_sel_rs1_m_l;
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assign sel_rs2_m = ~ecl_ecc_sel_rs2_m_l;
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assign sel_rs2_m = ~ecl_ecc_sel_rs2_m_l;
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assign sel_rs3_m = ~ecl_ecc_sel_rs3_m_l;
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assign sel_rs3_m = ~ecl_ecc_sel_rs3_m_l;
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