Subversion Repositories s1_core

// You should have received a copy of the GNU General Public

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// 

// ========== Copyright Header End ============================================

// ========== Copyright Header End ============================================

///////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////

//

//

//    Description:        Memory BIST Controller for the L1 ICache and DCache

//    Description:        Memory BIST Controller for the L1 ICache and DCache

//    Block Type:         Control Block

//    Block Type:         Control Block

//    Module:             mbist_engine

//    Module:             mbist_engine

//// reset buffer ////

//// reset buffer ////

   dffrl_async rstff(.din (grst_l),

   dffrl_async rstff(.din (grst_l),

                     .q   (mbist_reset_l),

                     .q   (mbist_reset_l),

                     .rst_l (arst_l));

                     .rst_l (arst_l));

   assign       mbist_reset = ~mbist_reset_l;

   assign       mbist_reset = ~mbist_reset_l;

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

//

//

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

               .clk      ( rclk                  ),

               .clk      ( rclk                  ),

               .din      ( config_in[7:0]       ),

               .din      ( config_in[7:0]       ),

  assign config_in[0]        =    mbist_start;

  assign config_in[0]        =    mbist_start;

  assign config_in[1]        =    config_out[0];

  assign config_in[1]        =    config_out[0];

  assign config_in[7]        =    start_transition   ?   mbist_loop_on_address:  config_out[7];

  assign config_in[7]        =    start_transition   ?   mbist_loop_on_address:  config_out[7];

  assign loop_on_address     =    config_out[7];

  assign loop_on_address     =    config_out[7];

                 .clk      ( rclk                    ),

                 .clk      ( rclk                    ),

                 .din      ( userdata_in[7:0]       ),

                 .din      ( userdata_in[7:0]       ),

  assign userdata_in[7:0]    =    userdata_out[7:0];

  assign userdata_in[7:0]    =    userdata_out[7:0];

                 .clk      ( rclk                   ),

                 .clk      ( rclk                   ),

                 .din      ( useradd_in[6:0]       ),

                 .din      ( useradd_in[6:0]       ),

  assign useradd_in[6:0]    =    useradd_out[6:0];

  assign useradd_in[6:0]    =    useradd_out[6:0];

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// Remove Address mix disable before delivery

// Remove Address mix disable before delivery

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

                      .clk   ( rclk                        ),

                      .clk   ( rclk                        ),

                      .din   ( control_in[20:0]           ),

                      .din   ( control_in[20:0]           ),

  assign   msb                       =     control_out[20];

  assign   msb                       =     control_out[20];

  assign   array_sel                 =     control_out[19];

  assign   array_sel                 =     control_out[19];

  assign   data_control[1:0]         =     userdata_mode ? 2'b11 : control_out[18:17];

  assign   data_control[1:0]         =     userdata_mode ? 2'b11 : control_out[18:17];

  assign   address_mix               =     loop_on_address    ?   1'b1:   control_out[16];

  assign   address_mix               =     loop_on_address    ?   1'b1:   control_out[16];

////////////////////////

////////////////////////

////////////////////////

////////////////////////

  assign msb_rst = msb & ~reset_engine;

  assign msb_rst = msb & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( msb_rst ),

                   .din      ( msb_rst ),

  assign msb_d1_rst = msb_d1 & ~reset_engine;

  assign msb_d1_rst = msb_d1 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( msb_d1_rst ),

                   .din      ( msb_d1_rst ),

  assign msb_d2_rst = msb_d2 & ~reset_engine;

  assign msb_d2_rst = msb_d2 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( msb_d2_rst ),

                   .din      ( msb_d2_rst ),

  assign msb_d3_rst = msb_d3 & ~reset_engine;

  assign msb_d3_rst = msb_d3 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( msb_d3_rst ),

                   .din      ( msb_d3_rst ),

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// Pipeline for Read, Data, and Address

// Pipeline for Read, Data, and Address

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

  wire ic_read_pipe_out1_bf, ic_read_pipe_out2_bf, ic_read_pipe_out3_bf;

  wire ic_read_pipe_out1_bf, ic_read_pipe_out2_bf, ic_read_pipe_out3_bf;

  ////////////

  ////////////

  ////////////

  ////////////

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( mbist_dcache_read      ),

                   .din      ( mbist_dcache_read      ),

  assign dc_read_pipe_out1_bf = dc_read_pipe_out1 & ~reset_engine;

  assign dc_read_pipe_out1_bf = dc_read_pipe_out1 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( dc_read_pipe_out1_bf   ),

                   .din      ( dc_read_pipe_out1_bf   ),

  assign dc_read_pipe_out2_bf = dc_read_pipe_out2 & ~reset_engine;

  assign dc_read_pipe_out2_bf = dc_read_pipe_out2 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( dc_read_pipe_out2_bf   ),

                   .din      ( dc_read_pipe_out2_bf   ),

  assign dc_read_pipe_out3_bf = dc_read_pipe_out3 & ~reset_engine;

  assign dc_read_pipe_out3_bf = dc_read_pipe_out3 & ~reset_engine;

  assign dcache_data_sel       =  dc_read_pipe_out3_bf;

  assign dcache_data_sel       =  dc_read_pipe_out3_bf;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( dc_read_pipe_out3_bf   ),

                   .din      ( dc_read_pipe_out3_bf   ),

  assign dcache_piped_read       =  dc_read_pipe_out4 & ~reset_engine;

  assign dcache_piped_read       =  dc_read_pipe_out4 & ~reset_engine;

  ////////////

  ////////////

  ////////////

  ////////////

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( mbist_icache_read_bf   ),

                   .din      ( mbist_icache_read_bf   ),

  assign ic_read_pipe_out1_bf = ic_read_pipe_out1 & ~reset_engine;

  assign ic_read_pipe_out1_bf = ic_read_pipe_out1 & ~reset_engine;

  assign mbist_icache_read = ic_read_pipe_out1;

  assign mbist_icache_read = ic_read_pipe_out1;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( ic_read_pipe_out1_bf   ),

                   .din      ( ic_read_pipe_out1_bf   ),

  assign ic_read_pipe_out2_bf = ic_read_pipe_out2 & ~reset_engine;

  assign ic_read_pipe_out2_bf = ic_read_pipe_out2 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( ic_read_pipe_out2_bf   ),

                   .din      ( ic_read_pipe_out2_bf   ),

  assign ic_read_pipe_out3_bf = ic_read_pipe_out3 & ~reset_engine;

  assign ic_read_pipe_out3_bf = ic_read_pipe_out3 & ~reset_engine;

                   .clk      ( rclk                   ),

                   .clk      ( rclk                   ),

                   .din      ( ic_read_pipe_out3_bf   ),

                   .din      ( ic_read_pipe_out3_bf   ),

  assign icache_piped_read       =  ic_read_pipe_out4 & ~reset_engine;

  assign icache_piped_read       =  ic_read_pipe_out4 & ~reset_engine;

  ////////////

  ////////////

  ////////////

  ////////////

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( mbist_icache_write_bf  ),

                   .din      ( mbist_icache_write_bf  ),

  ////////////

  ////////////

  ////////////

  ////////////

  wire [7:0] data_pipe_out3, data_pipe_out4;

  wire [7:0] data_pipe_out3, data_pipe_out4;

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( mbist_write_data_bf[7:0]  ),

                   .din      ( mbist_write_data_bf[7:0]  ),

  assign mbist_icache_wdata = data_pipe_out1;

  assign mbist_icache_wdata = data_pipe_out1;

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( data_pipe_out1[7:0]    ),

                   .din      ( data_pipe_out1[7:0]    ),

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( data_pipe_out2[7:0]    ),

                   .din      ( data_pipe_out2[7:0]    ),

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( data_pipe_out3[7:0]    ),

                   .din      ( data_pipe_out3[7:0]    ),

////////////

////////////

////////////

////////////

  wire [10:0] add_pipe_out3, add_pipe_out4;

  wire [10:0] add_pipe_out3, add_pipe_out4;

  wire mbist_word_sel_bf;

  wire mbist_word_sel_bf;

  assign mbist_word_sel_bf = loop_on_address ? useradd_out[6] : mbist_word_sel;

  assign mbist_word_sel_bf = loop_on_address ? useradd_out[6] : mbist_word_sel;

                   .clk      ( rclk                        ),

                   .clk      ( rclk                        ),

                   .din      ( {mbist_word_sel_bf, mbist_address_bf[9:0]}        ),

                   .din      ( {mbist_word_sel_bf, mbist_address_bf[9:0]}        ),

  assign mbist_address = add_pipe_out1;

  assign mbist_address = add_pipe_out1;

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( add_pipe_out1[10:0]    ),

                   .din      ( add_pipe_out1[10:0]    ),

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( add_pipe_out2[10:0]    ),

                   .din      ( add_pipe_out2[10:0]    ),

                   .clk      ( rclk                    ),

                   .clk      ( rclk                    ),

                   .din      ( add_pipe_out3[10:0]    ),

                   .din      ( add_pipe_out3[10:0]    ),

  assign dcache_piped_address[9:0]   =  {add_pipe_out4[10], add_pipe_out4[8:0]};

  assign dcache_piped_address[9:0]   =  {add_pipe_out4[10], add_pipe_out4[8:0]};

  assign icache_piped_address[10:0]  =  add_pipe_out4[10:0];

  assign icache_piped_address[10:0]  =  add_pipe_out4[10:0];

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// Shared Fail Detection

// Shared Fail Detection

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

                   .clk      ( rclk                ),

                   .clk      ( rclk                ),

                   .din      ( fail_reg_in[1:0]   ),

                   .din      ( fail_reg_in[1:0]   ),

  assign    fail_reg_in[1:0]      =    reset_engine      ?    2'b0: {qual_dcache_fail,qual_icache_fail}  |  fail_reg_out[1:0];

  assign    fail_reg_in[1:0]      =    reset_engine      ?    2'b0: {qual_dcache_fail,qual_icache_fail}  |  fail_reg_out[1:0];

                                (icache_piped_read ? {2{data_pipe_out4[1:0]}} : data_pipe_out4[3:0]), {7{data_pipe_out4[7:0]}},

                                (icache_piped_read ? {2{data_pipe_out4[1:0]}} : data_pipe_out4[3:0]), {7{data_pipe_out4[7:0]}},

                                (icache_piped_read ? data_pipe_out4[7:4] : data_pipe_out4[3:0]), data_pipe_out4[3:0] };

                                (icache_piped_read ? data_pipe_out4[7:4] : data_pipe_out4[3:0]), data_pipe_out4[3:0] };

  assign    compare_data_bf[71:0]    =    dcache_data_sel ?      mbist_dcache_data_in[71:0]:  {4'h0,mbist_icache_data_in[67:0]};

  assign    compare_data_bf[71:0]    =    dcache_data_sel ?      mbist_dcache_data_in[71:0]:  {4'h0,mbist_icache_data_in[67:0]};

                   .clk      ( rclk                        ),

                   .clk      ( rclk                        ),

                   .din      ( compare_data_bf[71:0]   ),

                   .din      ( compare_data_bf[71:0]   ),

  assign    mismatch              =    expect_data[71:0]   !=     compare_data[71:0];

  assign    mismatch              =    expect_data[71:0]   !=     compare_data[71:0];

  assign    mbist_dcache_fail     =    fail_reg_out[1];

  assign    mbist_dcache_fail     =    fail_reg_out[1];

// Fail Address and Data Capture and Control Reg Store

// Fail Address and Data Capture and Control Reg Store

// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

                   .clk      ( rclk                        ),

                   .clk      ( rclk                        ),

                   .din      ( fail_add_reg_in[10:0]   ),

                   .din      ( fail_add_reg_in[10:0]   ),

  assign fail_add_reg_in[10:0]     =  reset_engine              ?    11'b0:

  assign fail_add_reg_in[10:0]     =  reset_engine              ?    11'b0:

                                      qual_dcache_fail          ?    {1'b0,dcache_piped_address[9:0]}:

                                      qual_dcache_fail          ?    {1'b0,dcache_piped_address[9:0]}:

                                      qual_icache_fail          ?    icache_piped_address[10:0]:

                                      qual_icache_fail          ?    icache_piped_address[10:0]:

                                                                     fail_add_reg_out[10:0];

                                                                     fail_add_reg_out[10:0];

                   .clk      ( rclk                      ),

                   .clk      ( rclk                      ),

                   .din      ( fail_data_reg_in[71:0]   ),

                   .din      ( fail_data_reg_in[71:0]   ),

  assign fail_data_reg_in[71:0]     =  reset_engine     ?   72'b0:

  assign fail_data_reg_in[71:0]     =  reset_engine     ?   72'b0:

                                       qual_fail        ?   compare_data[71:0]:

                                       qual_fail        ?   compare_data[71:0]:

                                                            fail_data_reg_out[71:0];

                                                            fail_data_reg_out[71:0];

  assign fail_control_reg_in[20:0]     = (reset_engine && !mbist_stop_on_next_fail)    ?   21'b0:

  assign fail_control_reg_in[20:0]     = (reset_engine && !mbist_stop_on_next_fail)    ?   21'b0:

                                          qual_fail                                    ?   qual_control_out[20:0]:

                                          qual_fail                                    ?   qual_control_out[20:0]:

                                                                                           fail_control_reg_out[20:0];

                                                                                           fail_control_reg_out[20:0];

                   .clk      ( rclk                         ),

                   .clk      ( rclk                         ),

                   .din      ( fail_control_reg_in[20:0]   ),

                   .din      ( fail_control_reg_in[20:0]   ),

////////

////////

  assign  beyond_last_fail  =  qual_control_out[20:0]    >    fail_control_reg_out[20:0];

  assign  beyond_last_fail  =  qual_control_out[20:0]    >    fail_control_reg_out[20:0];