| Line 16... |
Line 16... |
// You should have received a copy of the GNU General Public
|
// You should have received a copy of the GNU General Public
|
// License along with this work; if not, write to the Free Software
|
// License along with this work; if not, write to the Free Software
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
//
|
//
|
// ========== Copyright Header End ============================================
|
// ========== Copyright Header End ============================================
|
|
`ifdef SIMPLY_RISC_TWEAKS
|
|
`define SIMPLY_RISC_SCANIN .si(0)
|
|
`else
|
|
`define SIMPLY_RISC_SCANIN .si()
|
|
`endif
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
/*
|
/*
|
// Module Name: sparc_ifu_swl
|
// Module Name: sparc_ifu_swl
|
// Description:
|
// Description:
|
// The switch logic manages the 4 threads. It schedules the next
|
// The switch logic manages the 4 threads. It schedules the next
|
// thread to be executed.
|
// thread to be executed.
|
*/
|
*/
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
|
|
/*
|
`include "ifu.h"
|
/* ========== Copyright Header Begin ==========================================
|
|
*
|
|
* OpenSPARC T1 Processor File: ifu.h
|
|
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
|
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
|
*
|
|
* The above named program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public
|
|
* License version 2 as published by the Free Software Foundation.
|
|
*
|
|
* The above named program is distributed in the hope that it will be
|
|
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public
|
|
* License along with this work; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
*
|
|
* ========== Copyright Header End ============================================
|
|
*/
|
|
////////////////////////////////////////////////////////////////////////
|
|
/*
|
|
//
|
|
// Module Name: ifu.h
|
|
// Description:
|
|
// All ifu defines
|
|
*/
|
|
|
|
//--------------------------------------------
|
|
// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP
|
|
//--------------------------------------------
|
|
// Set Values
|
|
|
|
// IC_IDX_HI = log(icache_size/4ways) - 1
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as
|
|
// well. Unfortunately this has not been properly parametrized.
|
|
// Changing the IC_LINE_SZ param alone is *not* enough.
|
|
|
|
|
|
// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as
|
|
// well. Changing the IC_TAG_HI param alone is *not* enough to
|
|
// change the PA range.
|
|
// highest bit of PA
|
|
|
|
|
|
|
|
// Derived Values
|
|
// 4095
|
|
|
|
|
|
// number of entries - 1 = 511
|
|
|
|
|
|
// 12
|
|
|
|
|
|
// 28
|
|
|
|
|
|
// 7
|
|
|
|
|
|
// tags for all 4 ways + parity
|
|
// 116
|
|
|
|
|
|
// 115
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For thread scheduler in IFU::DTU::SWL
|
|
//----------------------------------------------------------------------
|
|
// thread states: (thr_state[4:0])
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// thread configuration register bit fields
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// For MIL fsm in IFU::IFQ
|
|
//----------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------
|
|
// Interrupt Block
|
|
//---------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//-------------------------------------
|
|
// IFQ
|
|
//-------------------------------------
|
|
// valid bit plus ifill
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//`ifdef SPARC_L2_64B
|
|
|
|
|
|
//`else
|
|
//`define BANK_ID_HI 8
|
|
//`define BANK_ID_LO 7
|
|
//`endif
|
|
|
|
//`define CPX_INV_PA_HI 116
|
|
//`define CPX_INV_PA_LO 112
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------
|
|
// IFU Traps
|
|
//----------------------------------------
|
|
// precise
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// disrupting
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
module sparc_ifu_swl(/*AUTOARG*/
|
module sparc_ifu_swl(/*AUTOARG*/
|
// Outputs
|
// Outputs
|
swl_sscan_thrstate, so, dtu_reset, swl_dec_mulbusy_e,
|
swl_sscan_thrstate, so, dtu_reset, swl_dec_mulbusy_e,
|
swl_dec_divbusy_e, swl_dec_fpbusy_e, swl_dec_fp_enable_d,
|
swl_dec_divbusy_e, swl_dec_fpbusy_e, swl_dec_fp_enable_d,
|
| Line 236... |
Line 62... |
lsu_ifu_ldst_miss_g, fcl_swl_int_activate_i3,
|
lsu_ifu_ldst_miss_g, fcl_swl_int_activate_i3,
|
fcl_swl_flush_wake_w, ifq_swl_stallreq, fcl_dtu_stall_bf,
|
fcl_swl_flush_wake_w, ifq_swl_stallreq, fcl_dtu_stall_bf,
|
fcl_swl_swout_f, fcl_swl_swcvld_s, fdp_fcl_swc_s2,
|
fcl_swl_swout_f, fcl_swl_swcvld_s, fdp_fcl_swc_s2,
|
fcl_ifq_icmiss_s1, fcl_dtu_inst_vld_e, fcl_dtu_intr_vld_e,
|
fcl_ifq_icmiss_s1, fcl_dtu_inst_vld_e, fcl_dtu_intr_vld_e,
|
fcl_dtu_inst_vld_d, erb_dtu_ifeterr_d1, dtu_inst_anull_e,
|
fcl_dtu_inst_vld_d, erb_dtu_ifeterr_d1, dtu_inst_anull_e,
|
const_cpuid, thr_config_in_m,wbm_spc_stall,wbm_spc_resume, dec_swl_wrt_tcr_w,
|
const_cpuid, thr_config_in_m, dec_swl_wrt_tcr_w,
|
dec_swl_st_inst_d, extra_longlat_compl
|
dec_swl_st_inst_d, extra_longlat_compl
|
);
|
);
|
|
|
input rclk,
|
input rclk,
|
se,
|
se,
|
| Line 335... |
Line 161... |
input dtu_inst_anull_e; // anull delay slot
|
input dtu_inst_anull_e; // anull delay slot
|
|
|
input [3:0] const_cpuid; // use 4 bits to allow future
|
input [3:0] const_cpuid; // use 4 bits to allow future
|
// expansion to 16 cores
|
// expansion to 16 cores
|
|
|
input [2:0] thr_config_in_m;input wbm_spc_stall;input wbm_spc_resume;wire wait_state; // write data to thread status reg
|
input [2:0] thr_config_in_m; // write data to thread status reg
|
input dec_swl_wrt_tcr_w; // write signal for thr status reg
|
input dec_swl_wrt_tcr_w; // write signal for thr status reg
|
input dec_swl_st_inst_d;
|
input dec_swl_st_inst_d;
|
|
|
input [3:0] extra_longlat_compl; // spare signal, not used
|
input [3:0] extra_longlat_compl; // spare signal, not used
|
|
|
| Line 694... |
Line 520... |
assign clk = rclk;
|
assign clk = rclk;
|
|
|
// reset buffer
|
// reset buffer
|
dffrl_async rstff(.din (grst_l),
|
dffrl_async rstff(.din (grst_l),
|
.q (dtu_reset_l),
|
.q (dtu_reset_l),
|
.clk (clk), .se(se), .si(), .so(),
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),
|
.rst_l (arst_l));
|
.rst_l (arst_l));
|
|
|
assign dtu_reset = ~dtu_reset_l;
|
assign dtu_reset = ~dtu_reset_l;
|
|
|
|
|
| Line 707... |
Line 533... |
//---------------------------------------------
|
//---------------------------------------------
|
// dffr #(4) thrrdy_ctr(.din (count_nxt),
|
// dffr #(4) thrrdy_ctr(.din (count_nxt),
|
// .clk (clk),
|
// .clk (clk),
|
// .q (count),
|
// .q (count),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
//
|
//
|
// // count_nxt = count + 1, sticky at 8 = 1111
|
// // count_nxt = count + 1, sticky at 8 = 1111
|
// assign count_nxt[0] = ~count[0] | count[3];
|
// assign count_nxt[0] = ~count[0] | count[3];
|
// assign count_nxt[1] = (count[1] ^ count[0]) | count[3];
|
// assign count_nxt[1] = (count[1] ^ count[0]) | count[3];
|
// assign count_nxt[2] = (count[2] ^ (count[1] & count[0])) | count[3];
|
// assign count_nxt[2] = (count[2] ^ (count[1] & count[0])) | count[3];
|
| Line 730... |
Line 556... |
//`endif
|
//`endif
|
|
|
//-----------------
|
//-----------------
|
// completion logic
|
// completion logic
|
//-----------------
|
//-----------------
|
sparc_ifu_thrcmpl compl(.wbm_spc_stall(wbm_spc_stall),.wbm_spc_resume(wbm_spc_resume),.wait_state(wait_state),
|
sparc_ifu_thrcmpl compl(
|
.reset (dtu_reset),
|
.reset (dtu_reset),
|
/*AUTOINST*/
|
/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.completion (completion[3:0]),
|
.completion (completion[3:0]),
|
.wm_imiss (wm_imiss[3:0]),
|
.wm_imiss (wm_imiss[3:0]),
|
| Line 784... |
Line 610... |
|
|
// assign thr_dec_d[0] = thr_d[0] | rst_tri_en;
|
// assign thr_dec_d[0] = thr_d[0] | rst_tri_en;
|
// assign thr_dec_d[3:1] = thr_d[3:1] & {3{~rst_tri_en}};
|
// assign thr_dec_d[3:1] = thr_d[3:1] & {3{~rst_tri_en}};
|
|
|
|
|
dff #(4) thrd_reg(.din (thr_f[3:0]),
|
dff_s #(4) thrd_reg(.din (thr_f[3:0]),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_d[3:0]),
|
.q (thr_d[3:0]),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign swl_dcl_thr_d = thr_d;
|
assign swl_dcl_thr_d = thr_d;
|
|
|
dff #(4) thre_reg(.din (thr_d),
|
dff_s #(4) thre_reg(.din (thr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_e),
|
.q (thr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(4) thrm_reg(.din (thr_e),
|
dff_s #(4) thrm_reg(.din (thr_e),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_m),
|
.q (thr_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(4) thrw_reg(.din (thr_m),
|
dff_s #(4) thrw_reg(.din (thr_m),
|
.clk (clk),
|
.clk (clk),
|
.q (thr_w),
|
.q (thr_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(4) thrw2_reg(.din (thr_w),
|
dff_s #(4) thrw2_reg(.din (thr_w),
|
.clk (clk),
|
.clk (clk),
|
.q (st_thr_w2),
|
.q (st_thr_w2),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(4) thrw3_reg(.din (st_thr_w2),
|
dff_s #(4) thrw3_reg(.din (st_thr_w2),
|
.clk (clk),
|
.clk (clk),
|
.q (st_thr_w3),
|
.q (st_thr_w3),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign swl_dcl_thr_w2 = st_thr_w2;
|
assign swl_dcl_thr_w2 = st_thr_w2;
|
|
|
// send ibe of curr thread to dec
|
// send ibe of curr thread to dec
|
assign ibe_d = (thr_d[0] & tlu_hpstate_ibe[0] |
|
assign ibe_d = (thr_d[0] & tlu_hpstate_ibe[0] |
|
thr_d[1] & tlu_hpstate_ibe[1] |
|
thr_d[1] & tlu_hpstate_ibe[1] |
|
thr_d[2] & tlu_hpstate_ibe[2] |
|
thr_d[2] & tlu_hpstate_ibe[2] |
|
thr_d[3] & tlu_hpstate_ibe[3]);
|
thr_d[3] & tlu_hpstate_ibe[3]);
|
|
|
dff #(1) ibee_ff(.din (ibe_d),
|
dff_s #(1) ibee_ff(.din (ibe_d),
|
.q (ibe_e),
|
.q (ibe_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign swl_dec_ibe_e = ibe_e;
|
assign swl_dec_ibe_e = ibe_e;
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Track Thread Execution
|
// Track Thread Execution
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
|
// track instructions
|
// track instructions
|
dff #(1) lle_ff(.din (dec_swl_ll_done_d),
|
dff_s #(1) lle_ff(.din (dec_swl_ll_done_d),
|
.q (llinst_done_e),
|
.q (llinst_done_e),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign ll_done_e = thr_e & {4{llinst_done_e & fcl_dtu_inst_vld_e &
|
assign ll_done_e = thr_e & {4{llinst_done_e & fcl_dtu_inst_vld_e &
|
~exu_ifu_spill_e}};
|
~exu_ifu_spill_e}};
|
assign std_tcc_done_m = thr_m & {4{dcl_swl_tcc_done_m | std_done_m}};
|
assign std_tcc_done_m = thr_m & {4{dcl_swl_tcc_done_m | std_done_m}};
|
|
|
assign wsr_fixed_qual_w = wsr_fixed_inst_w & ifu_tlu_inst_vld_w &
|
assign wsr_fixed_qual_w = wsr_fixed_inst_w & ifu_tlu_inst_vld_w &
|
~fcl_swl_flush_w;
|
~fcl_swl_flush_w;
|
dff #(1) wsrw2_ff(.din (wsr_fixed_qual_w),
|
dff_s #(1) wsrw2_ff(.din (wsr_fixed_qual_w),
|
.q (wsr_fixed_w2),
|
.q (wsr_fixed_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign wsr_inst_w2 = wsr_fixed_w2 & ~flush_pipe_w2;
|
assign wsr_inst_w2 = wsr_fixed_w2 & ~flush_pipe_w2;
|
|
|
// delay one cycle to allow tlu to finish
|
// delay one cycle to allow tlu to finish
|
dff #(1) wsw3_ff(.din (wsr_inst_w2),
|
dff_s #(1) wsw3_ff(.din (wsr_inst_w2),
|
.q (wsr_inst_w3),
|
.q (wsr_inst_w3),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign wsr_done_w3 = {4{wsr_inst_w3}} & st_thr_w3;
|
assign wsr_done_w3 = {4{wsr_inst_w3}} & st_thr_w3;
|
|
|
assign fixedop_done = (ll_done_e | wsr_done_w3 | std_tcc_done_m |
|
assign fixedop_done = (ll_done_e | wsr_done_w3 | std_tcc_done_m |
|
wrt_tcr_w2 | extra_longlat_compl);
|
wrt_tcr_w2 | extra_longlat_compl);
|
| Line 865... |
Line 691... |
|
|
assign sta_done_e = dec_swl_sta_inst_e & fcl_dtu_inst_vld_e &
|
assign sta_done_e = dec_swl_sta_inst_e & fcl_dtu_inst_vld_e &
|
~lsu_ifu_ldsta_internal_e;
|
~lsu_ifu_ldsta_internal_e;
|
assign ld_inst_qual_d = dec_swl_ld_inst_d & fcl_dtu_inst_vld_d &
|
assign ld_inst_qual_d = dec_swl_ld_inst_d & fcl_dtu_inst_vld_d &
|
~iferr_d;
|
~iferr_d;
|
dff #(1) lde_ff(.din (ld_inst_qual_d),
|
dff_s #(1) lde_ff(.din (ld_inst_qual_d),
|
.clk (clk),
|
.clk (clk),
|
.q (ld_inst_e),
|
.q (ld_inst_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign ld_inst_next_e = ld_inst_e;
|
assign ld_inst_next_e = ld_inst_e;
|
// & ~dtu_inst_anull_e &
|
// & ~dtu_inst_anull_e &
|
// ~(lsu_ifu_ldsta_internal_e &
|
// ~(lsu_ifu_ldsta_internal_e &
|
// ifu_lsu_alt_space_e &
|
// ifu_lsu_alt_space_e &
|
// fcl_dtu_inst_vld_e);
|
// fcl_dtu_inst_vld_e);
|
| Line 880... |
Line 706... |
// assign ld_inst_internal_e = ~dtu_inst_anull_e & ld_inst_e &
|
// assign ld_inst_internal_e = ~dtu_inst_anull_e & ld_inst_e &
|
// (fcl_dtu_inst_vld_e &
|
// (fcl_dtu_inst_vld_e &
|
// lsu_ifu_ldsta_internal_e &
|
// lsu_ifu_ldsta_internal_e &
|
// ifu_lsu_alt_space_e);
|
// ifu_lsu_alt_space_e);
|
|
|
dff #(1) ldm_ff(.din (ld_inst_next_e),
|
dff_s #(1) ldm_ff(.din (ld_inst_next_e),
|
.clk (clk),
|
.clk (clk),
|
.q (ld_inst_m),
|
.q (ld_inst_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) ldw_ff(.din (ld_inst_m),
|
dff_s #(1) ldw_ff(.din (ld_inst_m),
|
.clk (clk),
|
.clk (clk),
|
.q (ld_inst_unq_w),
|
.q (ld_inst_unq_w),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign ld_inst_w = ifu_tlu_inst_vld_w & ld_inst_unq_w;
|
assign ld_inst_w = ifu_tlu_inst_vld_w & ld_inst_unq_w;
|
dff #(1) ldw2_ff(.din (ld_inst_w),
|
dff_s #(1) ldw2_ff(.din (ld_inst_w),
|
.clk (clk),
|
.clk (clk),
|
.q (ld_inst_w2),
|
.q (ld_inst_w2),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// track instruction status
|
// track instruction status
|
dff #(1) swcd_ff(.din (sw_cond_s),
|
dff_s #(1) swcd_ff(.din (sw_cond_s),
|
.clk (clk),
|
.clk (clk),
|
.q (swc_d),
|
.q (swc_d),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign swc_next_d = (swc_d & ~dec_swl_br_done_d);
|
assign swc_next_d = (swc_d & ~dec_swl_br_done_d);
|
// | fcl_dtu_sync_intr_d;
|
// | fcl_dtu_sync_intr_d;
|
|
|
dff #(1) swce_ff(.din (swc_next_d),
|
dff_s #(1) swce_ff(.din (swc_next_d),
|
.clk (clk),
|
.clk (clk),
|
.q (swc_e),
|
.q (swc_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//bug6838,bug6989 - interrupt issued in annulled delay slot resets wm_other mask in e-stage; this
|
//bug6838,bug6989 - interrupt issued in annulled delay slot resets wm_other mask in e-stage; this
|
// reset causes switch logic to lose a long latency op(div) which set the wm_other mask
|
// reset causes switch logic to lose a long latency op(div) which set the wm_other mask
|
// in s-stage. Note that the div is issued to FPU. the ifu re-issues the interrupt -
|
// in s-stage. Note that the div is issued to FPU. the ifu re-issues the interrupt -
|
// which results in flush. this kills the long latency op and div is lost
|
// which results in flush. this kills the long latency op and div is lost
|
| Line 931... |
Line 757... |
// a uniop is something that stalls all threads (looks like a uni
|
// a uniop is something that stalls all threads (looks like a uni
|
// threaded machine)
|
// threaded machine)
|
assign uniop_d = (dec_swl_allfp_d | //& swl_dec_fp_enable_d
|
assign uniop_d = (dec_swl_allfp_d | //& swl_dec_fp_enable_d
|
dec_swl_mul_inst_d | dec_swl_div_inst_d) &
|
dec_swl_mul_inst_d | dec_swl_div_inst_d) &
|
fcl_dtu_inst_vld_d;
|
fcl_dtu_inst_vld_d;
|
dff #(1) uniop_ff(.din (uniop_d),
|
dff_s #(1) uniop_ff(.din (uniop_d),
|
.clk (clk),
|
.clk (clk),
|
.q (uniop_e),
|
.q (uniop_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign killed_uniop_done_e = thr_e & {4{dtu_inst_anull_e & uniop_e &
|
assign killed_uniop_done_e = thr_e & {4{dtu_inst_anull_e & uniop_e &
|
fcl_dtu_inst_vld_e |
|
fcl_dtu_inst_vld_e |
|
clear_wmo_e}};
|
clear_wmo_e}};
|
|
|
// assign sched_nt = fcl_dtu_switch_s & ~fcl_dtu_stall_bf;
|
// assign sched_nt = fcl_dtu_switch_s & ~fcl_dtu_stall_bf;
|
| Line 983... |
Line 809... |
assign ldmiss = ldmiss_crit | ldmiss_non_crit;
|
assign ldmiss = ldmiss_crit | ldmiss_non_crit;
|
|
|
assign rt_st_thr_d = thr_d & {4{retract_store_d}};
|
assign rt_st_thr_d = thr_d & {4{retract_store_d}};
|
assign rt_st_thr_e = thr_e & {4{retract_store_e}};
|
assign rt_st_thr_e = thr_e & {4{retract_store_e}};
|
|
|
dff #(1) rbw2_ff(.din (rollback_g),
|
dff_s #(1) rbw2_ff(.din (rollback_g),
|
.q (rollback_w2),
|
.q (rollback_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// traps and interrupts
|
// traps and interrupts
|
dff #(1) ld_trp_reg(.din (tlu_ifu_trappc_vld_w1),
|
dff_s #(1) ld_trp_reg(.din (tlu_ifu_trappc_vld_w1),
|
.q (trappc_vld_w2),
|
.q (trappc_vld_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(2) trp_tid_reg(.din (tlu_ifu_trap_tid_w1[1:0]),
|
dff_s #(2) trp_tid_reg(.din (tlu_ifu_trap_tid_w1[1:0]),
|
.q (trap_tid_w2[1:0]),
|
.q (trap_tid_w2[1:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign trap_thr[0] = ~trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[0] = ~trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[1] = ~trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[1] = ~trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[2] = trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[2] = trap_tid_w2[1] & ~trap_tid_w2[0];
|
assign trap_thr[3] = trap_tid_w2[1] & trap_tid_w2[0];
|
assign trap_thr[3] = trap_tid_w2[1] & trap_tid_w2[0];
|
| Line 1009... |
Line 835... |
assign rbfor_fst_ce_w = ifu_tlu_inst_vld_w & ~tlu_ifu_flush_pipe_w &
|
assign rbfor_fst_ce_w = ifu_tlu_inst_vld_w & ~tlu_ifu_flush_pipe_w &
|
ffu_ifu_fst_ce_w & ~fcl_swl_flush_w;
|
ffu_ifu_fst_ce_w & ~fcl_swl_flush_w;
|
|
|
// dff #(1) fstce_ff(.din (rbfor_fst_ce_w),
|
// dff #(1) fstce_ff(.din (rbfor_fst_ce_w),
|
// .q (rbfor_fst_ce_w2),
|
// .q (rbfor_fst_ce_w2),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign flush_all_w = tlu_ifu_flush_pipe_w | fcl_swl_flush_w;
|
assign flush_all_w = tlu_ifu_flush_pipe_w | fcl_swl_flush_w;
|
// assign flush_pipe_w_nxt = tlu_ifu_flush_pipe_w & ~fcl_swl_flush_w;
|
// assign flush_pipe_w_nxt = tlu_ifu_flush_pipe_w & ~fcl_swl_flush_w;
|
assign flush_pipe_w_nxt = tlu_ifu_flush_pipe_w &
|
assign flush_pipe_w_nxt = tlu_ifu_flush_pipe_w &
|
~fcl_swl_flush_wake_w;
|
~fcl_swl_flush_wake_w;
|
|
|
dff #(1) flpw2_ff(.din (flush_pipe_w_nxt),
|
dff_s #(1) flpw2_ff(.din (flush_pipe_w_nxt),
|
.q (flush_pipe_w2),
|
.q (flush_pipe_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign no_iftrap_m = ~ifu_tlu_ttype_vld_m;
|
// assign no_iftrap_m = ~ifu_tlu_ttype_vld_m;
|
// dff #(1) trpw_ff(.din (no_iftrap_m),
|
// dff #(1) trpw_ff(.din (no_iftrap_m),
|
// .q (no_iftrap_w),
|
// .q (no_iftrap_w),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
//bug6838,bug6989 - change setting of trap for interrupt from d-cycle to e-cycle
|
//bug6838,bug6989 - change setting of trap for interrupt from d-cycle to e-cycle
|
// remove thr_d & {4{fcl_dtu_sync_intr_d & ~iferr_d}} & ~rt_st_thr_e |
|
// remove thr_d & {4{fcl_dtu_sync_intr_d & ~iferr_d}} & ~rt_st_thr_e |
|
|
|
// assign trap = thr_w & {4{flush_all_w}} |
|
// assign trap = thr_w & {4{flush_all_w}} |
|
| Line 1050... |
Line 876... |
thr_d[2] & trp_no_retr[2] |
|
thr_d[2] & trp_no_retr[2] |
|
thr_d[3] & trp_no_retr[3]);
|
thr_d[3] & trp_no_retr[3]);
|
|
|
// assign flush_done_w = fcl_swl_flush_w & ~fcl_swl_flush_wait_w;
|
// assign flush_done_w = fcl_swl_flush_w & ~fcl_swl_flush_wait_w;
|
assign flush_done_w = fcl_swl_flush_wake_w;
|
assign flush_done_w = fcl_swl_flush_wake_w;
|
dff #(1) flsh_ff(.din (flush_done_w),
|
dff_s #(1) flsh_ff(.din (flush_done_w),
|
.q (flush_done_w2),
|
.q (flush_done_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign flush_wake_w2 = {4{flush_done_w2}} & st_thr_w2 | fp_flush_wake_w3;
|
assign flush_wake_w2 = {4{flush_done_w2}} & st_thr_w2 | fp_flush_wake_w3;
|
|
|
// delay FP wakeup by one extra cycle to allow time for IRF CE
|
// delay FP wakeup by one extra cycle to allow time for IRF CE
|
// to be corrected.
|
// to be corrected.
|
dff #(1) fpflsh_ff(.din (rbfor_fst_ce_w),
|
dff_s #(1) fpflsh_ff(.din (rbfor_fst_ce_w),
|
.q (fp_flush_done_w2),
|
.q (fp_flush_done_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) fpflw_ff(.din (fp_flush_done_w2),
|
dff_s #(1) fpflw_ff(.din (fp_flush_done_w2),
|
.q (fp_flush_done_w3),
|
.q (fp_flush_done_w3),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fp_flush_wake_w3 = st_thr_w3 & {4{fp_flush_done_w3}};
|
assign fp_flush_wake_w3 = st_thr_w3 & {4{fp_flush_done_w3}};
|
|
|
// store buffer full
|
// store buffer full
|
// assign stbfull_on_curr_thr = stb_stall & thr_f;
|
// assign stbfull_on_curr_thr = stb_stall & thr_f;
|
// assign stbfull_thisthr = stbfull_on_curr_thr[0] |
|
// assign stbfull_thisthr = stbfull_on_curr_thr[0] |
|
| Line 1127... |
Line 953... |
//`ifdef IFU_SAT
|
//`ifdef IFU_SAT
|
// assign start_thread = {3'b0, start_on_rst} | auto_start |
|
// assign start_thread = {3'b0, start_on_rst} | auto_start |
|
// resum_thread & (~wm_imiss | ifq_dtu_thrrdy);
|
// resum_thread & (~wm_imiss | ifq_dtu_thrrdy);
|
//`else
|
//`else
|
assign start_thread = resum_thread & (~wm_imiss | ifq_dtu_thrrdy) &
|
assign start_thread = resum_thread & (~wm_imiss | ifq_dtu_thrrdy) &
|
(~wm_stbwait|stb_retry)&(~wait_state|wbm_spc_resume);
|
(~wm_stbwait | stb_retry);
|
assign thaw_thread = resum_thread & (wm_imiss & ~ifq_dtu_thrrdy |
|
assign thaw_thread = resum_thread & (wm_imiss & ~ifq_dtu_thrrdy |
|
wm_stbwait & ~stb_retry|wait_state & ~wbm_spc_resume);
|
wm_stbwait & ~stb_retry);
|
|
|
//`endif
|
//`endif
|
|
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Thread FSM
|
// Thread FSM
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
sparc_ifu_thrfsm thrfsm0(
|
sparc_ifu_thrfsm thrfsm0(
|
// Outputs
|
// Outputs
|
|
`ifdef FPGA_SYN
|
|
|
.so (/*so*/),
|
.so (/*so*/),
|
|
`else
|
|
.so (so),
|
|
`endif
|
.thr_state (thr0_state[4:0]),
|
.thr_state (thr0_state[4:0]),
|
// Inputs
|
// Inputs
|
.completion(completion[0]),
|
.completion(completion[0]),
|
.schedule (schedule[0]),
|
.schedule (schedule[0]),
|
.spec_ld (issue_spec_ld[0]),
|
.spec_ld (issue_spec_ld[0]),
|
| Line 1171... |
Line 997... |
.si (si),
|
.si (si),
|
.reset (dtu_reset));
|
.reset (dtu_reset));
|
|
|
sparc_ifu_thrfsm thrfsm1(
|
sparc_ifu_thrfsm thrfsm1(
|
// Outputs
|
// Outputs
|
|
`ifdef FPGA_SYN
|
|
|
.so (/*so*/),
|
.so (/*so*/),
|
|
`else
|
|
.so (so),
|
|
`endif
|
.thr_state (thr1_state[4:0]),
|
.thr_state (thr1_state[4:0]),
|
// Inputs
|
// Inputs
|
.completion(completion[1]),
|
.completion(completion[1]),
|
.schedule (schedule[1]),
|
.schedule (schedule[1]),
|
.spec_ld (issue_spec_ld[1]),
|
.spec_ld (issue_spec_ld[1]),
|
| Line 1203... |
Line 1029... |
.si (si),
|
.si (si),
|
.reset (dtu_reset));
|
.reset (dtu_reset));
|
|
|
sparc_ifu_thrfsm thrfsm2(
|
sparc_ifu_thrfsm thrfsm2(
|
// Outputs
|
// Outputs
|
|
`ifdef FPGA_SYN
|
|
|
.so (/*so*/),
|
.so (/*so*/),
|
|
`else
|
|
.so (so),
|
|
`endif
|
.thr_state (thr2_state[4:0]),
|
.thr_state (thr2_state[4:0]),
|
// Inputs
|
// Inputs
|
.completion(completion[2]),
|
.completion(completion[2]),
|
.schedule (schedule[2]),
|
.schedule (schedule[2]),
|
.spec_ld (issue_spec_ld[2]),
|
.spec_ld (issue_spec_ld[2]),
|
| Line 1235... |
Line 1061... |
.si (si),
|
.si (si),
|
.reset (dtu_reset));
|
.reset (dtu_reset));
|
|
|
sparc_ifu_thrfsm thrfsm3(
|
sparc_ifu_thrfsm thrfsm3(
|
// Outputs
|
// Outputs
|
|
`ifdef FPGA_SYN
|
|
|
.so (/*so*/),
|
.so (/*so*/),
|
|
`else
|
|
.so (so),
|
|
`endif
|
.thr_state (thr3_state[4:0]),
|
.thr_state (thr3_state[4:0]),
|
// Inputs
|
// Inputs
|
.completion(completion[3]),
|
.completion(completion[3]),
|
.schedule (schedule[3]),
|
.schedule (schedule[3]),
|
.spec_ld (issue_spec_ld[3]),
|
.spec_ld (issue_spec_ld[3]),
|
| Line 1269... |
Line 1095... |
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// Schedule Next Thread
|
// Schedule Next Thread
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
// rdy bit from thrfsm
|
// rdy bit from thrfsm
|
assign dtu_fcl_thr_active[0] = thr0_state[0];
|
assign dtu_fcl_thr_active[0] = thr0_state[`TCR_ACTIVE];
|
assign dtu_fcl_thr_active[1] = thr1_state[0];
|
assign dtu_fcl_thr_active[1] = thr1_state[`TCR_ACTIVE];
|
assign dtu_fcl_thr_active[2] = thr2_state[0];
|
assign dtu_fcl_thr_active[2] = thr2_state[`TCR_ACTIVE];
|
assign dtu_fcl_thr_active[3] = thr3_state[0];
|
assign dtu_fcl_thr_active[3] = thr3_state[`TCR_ACTIVE];
|
|
|
assign rdy[0] = thr0_state[3];
|
assign rdy[0] = thr0_state[`TCR_URDY];
|
assign rdy[1] = thr1_state[3];
|
assign rdy[1] = thr1_state[`TCR_URDY];
|
assign rdy[2] = thr2_state[3];
|
assign rdy[2] = thr2_state[`TCR_URDY];
|
assign rdy[3] = thr3_state[3];
|
assign rdy[3] = thr3_state[`TCR_URDY];
|
|
|
assign sprdy_or_urdy[0] = thr0_state[4];
|
assign sprdy_or_urdy[0] = thr0_state[`TCR_READY];
|
assign sprdy_or_urdy[1] = thr1_state[4];
|
assign sprdy_or_urdy[1] = thr1_state[`TCR_READY];
|
assign sprdy_or_urdy[2] = thr2_state[4];
|
assign sprdy_or_urdy[2] = thr2_state[`TCR_READY];
|
assign sprdy_or_urdy[3] = thr3_state[4];
|
assign sprdy_or_urdy[3] = thr3_state[`TCR_READY];
|
|
|
assign running_s2 = (thr0_state[2] |
|
assign running_s2 = (thr0_state[`TCR_RUNNING] |
|
thr1_state[2] |
|
thr1_state[`TCR_RUNNING] |
|
thr2_state[2] |
|
thr2_state[`TCR_RUNNING] |
|
thr3_state[2]);
|
thr3_state[`TCR_RUNNING]);
|
|
|
assign dtu_fcl_running_s = running_s2;
|
assign dtu_fcl_running_s = running_s2;
|
|
|
assign thr_s2 = {thr3_state[2],
|
assign thr_s2 = {thr3_state[`TCR_RUNNING],
|
thr2_state[2],
|
thr2_state[`TCR_RUNNING],
|
thr1_state[2],
|
thr1_state[`TCR_RUNNING],
|
thr0_state[2]};
|
thr0_state[`TCR_RUNNING]};
|
|
|
// Next Thread Ready
|
// Next Thread Ready
|
assign dtu_fcl_ntr_s = (sprdy_or_urdy[0] | sprdy_or_urdy[1] |
|
assign dtu_fcl_ntr_s = (sprdy_or_urdy[0] | sprdy_or_urdy[1] |
|
sprdy_or_urdy[2] | sprdy_or_urdy[3]);
|
sprdy_or_urdy[2] | sprdy_or_urdy[3]);
|
|
|
| Line 1335... |
Line 1161... |
assign rd_thract_d = (thr0_state[0] & thr_d[0] |
|
assign rd_thract_d = (thr0_state[0] & thr_d[0] |
|
thr1_state[0] & thr_d[1] |
|
thr1_state[0] & thr_d[1] |
|
thr2_state[0] & thr_d[2] |
|
thr2_state[0] & thr_d[2] |
|
thr3_state[0] & thr_d[3]);
|
thr3_state[0] & thr_d[3]);
|
|
|
dff #(1) rdthr_ff(.din (rd_thract_d),
|
dff_s #(1) rdthr_ff(.din (rd_thract_d),
|
.clk (clk),
|
.clk (clk),
|
.q (rd_thract_e),
|
.q (rd_thract_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(3) rdcf_reg(.din ({enc_thr_d, en_spec_d}),
|
dff_s #(3) rdcf_reg(.din ({enc_thr_d, en_spec_d}),
|
.clk (clk),
|
.clk (clk),
|
.q (rd_tid_spec_e),
|
.q (rd_tid_spec_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) hpe_ff(.din (fcl_dtu_hprivmode_d),
|
dff_s #(1) hpe_ff(.din (fcl_dtu_hprivmode_d),
|
.clk (clk),
|
.clk (clk),
|
.q (hprivmode_e),
|
.q (hprivmode_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(1) rdthre_ff(.din (dec_swl_rdsr_sel_thr_d),
|
dff_s #(1) rdthre_ff(.din (dec_swl_rdsr_sel_thr_d),
|
.clk (clk),
|
.clk (clk),
|
.q (rdsr_sel_thr_e),
|
.q (rdsr_sel_thr_e),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// TBD: read out all thread state, not just the current thread
|
// TBD: read out all thread state, not just the current thread
|
// Done 9/26/02
|
// Done 9/26/02
|
assign fmt_thrconf_e = {wm_stbwait,
|
assign fmt_thrconf_e = {wm_stbwait,
|
wm_other,
|
wm_other,
|
| Line 1441... |
Line 1267... |
thr_config_in_w2[2] :
|
thr_config_in_w2[2] :
|
en_spec_d;
|
en_spec_d;
|
|
|
assign halt_w = wrt_spec_w & ~thr_config_in_w[0];
|
assign halt_w = wrt_spec_w & ~thr_config_in_w[0];
|
|
|
dff #(1) wrsw2_ff(.din (wrt_spec_w),
|
dff_s #(1) wrsw2_ff(.din (wrt_spec_w),
|
.q (wrt_spec_w2),
|
.q (wrt_spec_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign wrt_tcr_w2 = st_thr_w2 & {4{wrt_spec_w2}};
|
assign wrt_tcr_w2 = st_thr_w2 & {4{wrt_spec_w2}};
|
|
|
dff #(1) hlt_ff(.din (halt_w),
|
dff_s #(1) hlt_ff(.din (halt_w),
|
.q (halt_w2),
|
.q (halt_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign halt_thread = st_thr_w2 & {4{halt_w2}};
|
assign halt_thread = st_thr_w2 & {4{halt_w2}};
|
|
|
dffr #(1) enspec_ff(.din (spec_next),
|
dffr_s #(1) enspec_ff(.din (spec_next),
|
.clk (clk),
|
.clk (clk),
|
.q (en_spec_d),
|
.q (en_spec_d),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) enspecm_ff(.din (rd_tid_spec_e[0]),
|
dff_s #(1) enspecm_ff(.din (rd_tid_spec_e[0]),
|
.clk (clk),
|
.clk (clk),
|
.q (en_spec_m),
|
.q (en_spec_m),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(1) enspecw_ff(.din (en_spec_m),
|
dff_s #(1) enspecw_ff(.din (en_spec_m),
|
.clk (clk),
|
.clk (clk),
|
.q (en_spec_g),
|
.q (en_spec_g),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
|
|
//-----------------------------
|
//-----------------------------
|
// Instruction Flow Control
|
// Instruction Flow Control
|
//-----------------------------
|
//-----------------------------
|
| Line 1495... |
Line 1321... |
~rt_st_thr_d & ~rt_st_thr_e |
|
~rt_st_thr_d & ~rt_st_thr_e |
|
// FP could be a st
|
// FP could be a st
|
fp_busy_e & ~killed_uniop_done_e) &
|
fp_busy_e & ~killed_uniop_done_e) &
|
{4{~ffu_ifu_fpop_done_w2}} & ~trp_no_retr; // reset wins
|
{4{~ffu_ifu_fpop_done_w2}} & ~trp_no_retr; // reset wins
|
|
|
dffr #(4) mulb_ff(.din (mul_busy_d),
|
dffr_s #(4) mulb_ff(.din (mul_busy_d),
|
.q (mul_busy_e),
|
.q (mul_busy_e),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign true_mulbusy_e = (|mul_busy_e[3:0]);
|
assign true_mulbusy_e = (|mul_busy_e[3:0]);
|
assign mbusy_d0 = true_mulbusy_e & mul_wait_any;
|
assign mbusy_d0 = true_mulbusy_e & mul_wait_any;
|
|
|
// block shared resource for two extra cycles, to allow waiting
|
// block shared resource for two extra cycles, to allow waiting
|
// threads a fair chance at getting it.
|
// threads a fair chance at getting it.
|
assign swl_dec_mulbusy_e = true_mulbusy_e | mbusy_d3 | mbusy_d1 | mbusy_d2;
|
assign swl_dec_mulbusy_e = true_mulbusy_e | mbusy_d3 | mbusy_d1 | mbusy_d2;
|
|
|
dffr #(4) divb_ff(.din (div_busy_d),
|
dffr_s #(4) divb_ff(.din (div_busy_d),
|
.q (div_busy_e),
|
.q (div_busy_e),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign true_divbusy_e = (|div_busy_e[3:0]);
|
assign true_divbusy_e = (|div_busy_e[3:0]);
|
assign dbusy_d0 = true_divbusy_e & div_wait_any;
|
assign dbusy_d0 = true_divbusy_e & div_wait_any;
|
|
|
// block shared resource for two extra cycles, to allow waiting
|
// block shared resource for two extra cycles, to allow waiting
|
// threads a fair chance at getting it.
|
// threads a fair chance at getting it.
|
assign swl_dec_divbusy_e = true_divbusy_e | dbusy_d3 | dbusy_d1 | dbusy_d2;
|
assign swl_dec_divbusy_e = true_divbusy_e | dbusy_d3 | dbusy_d1 | dbusy_d2;
|
|
|
dffr #(4) fpb_ff(.din (fp_busy_d),
|
dffr_s #(4) fpb_ff(.din (fp_busy_d),
|
.q (fp_busy_e),
|
.q (fp_busy_e),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign true_fpbusy_e = (|fp_busy_e[3:0]);
|
assign true_fpbusy_e = (|fp_busy_e[3:0]);
|
assign fbusy_d0 = true_fpbusy_e & fp_wait_any;
|
assign fbusy_d0 = true_fpbusy_e & fp_wait_any;
|
|
|
assign fbusy_nxt_d = (|fp_busy_d[3:0]) | fbusy_d0 | fbusy_d1 | fbusy_d2;
|
assign fbusy_nxt_d = (|fp_busy_d[3:0]) | fbusy_d0 | fbusy_d1 | fbusy_d2;
|
dffr #(1) tfbe_ff(.din (fbusy_nxt_d),
|
dffr_s #(1) tfbe_ff(.din (fbusy_nxt_d),
|
.q (fbusy_crit_e),
|
.q (fbusy_crit_e),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset), .se(se), .si(), .so());
|
.rst (dtu_reset), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// block shared resource for two extra cycles, to allow waiting
|
// block shared resource for two extra cycles, to allow waiting
|
// threads a fair chance at getting it.
|
// threads a fair chance at getting it.
|
assign swl_dec_fpbusy_e = fbusy_crit_e;
|
assign swl_dec_fpbusy_e = fbusy_crit_e;
|
assign fpbusy_local_e = true_fpbusy_e | fbusy_d3 | fbusy_d1 | fbusy_d2;
|
assign fpbusy_local_e = true_fpbusy_e | fbusy_d3 | fbusy_d1 | fbusy_d2;
|
|
|
dff #(3) bd1_reg(.din ({mbusy_d0, dbusy_d0, fbusy_d0}),
|
dff_s #(3) bd1_reg(.din ({mbusy_d0, dbusy_d0, fbusy_d0}),
|
.q ({mbusy_d1, dbusy_d1, fbusy_d1}),
|
.q ({mbusy_d1, dbusy_d1, fbusy_d1}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(3) bd2_reg(.din ({mbusy_d1, dbusy_d1, fbusy_d1}),
|
dff_s #(3) bd2_reg(.din ({mbusy_d1, dbusy_d1, fbusy_d1}),
|
.q ({mbusy_d2, dbusy_d2, fbusy_d2}),
|
.q ({mbusy_d2, dbusy_d2, fbusy_d2}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(3) bd3_reg(.din ({mbusy_d2, dbusy_d2, fbusy_d2}),
|
dff_s #(3) bd3_reg(.din ({mbusy_d2, dbusy_d2, fbusy_d2}),
|
.q ({mbusy_d3, dbusy_d3, fbusy_d3}),
|
.q ({mbusy_d3, dbusy_d3, fbusy_d3}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// ifetch errors
|
// ifetch errors
|
// If there was an error in the ifetch call back this instruction
|
// If there was an error in the ifetch call back this instruction
|
assign iferr_d = erb_dtu_ifeterr_d1 & same_thr_de;
|
assign iferr_d = erb_dtu_ifeterr_d1 & same_thr_de;
|
assign iferr_s = erb_dtu_ifeterr_d1 & same_thr_fe;
|
assign iferr_s = erb_dtu_ifeterr_d1 & same_thr_fe;
|
| Line 1583... |
Line 1409... |
fcl_dtu_inst_vld_d & ~iferr_d}} &
|
fcl_dtu_inst_vld_d & ~iferr_d}} &
|
thr_d & ~rt_st_thr_e | mul_done | // set
|
thr_d & ~rt_st_thr_e | mul_done | // set
|
mul_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
mul_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
(~trp_no_retr);
|
(~trp_no_retr);
|
|
|
dffr #(4) mw_ff(.din (mul_wait_nxt[3:0]),
|
dffr_s #(4) mw_ff(.din (mul_wait_nxt[3:0]),
|
.q (mul_wait[3:0]),
|
.q (mul_wait[3:0]),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign mul_wait_any = (|mul_wait[3:0]);
|
assign mul_wait_any = (|mul_wait[3:0]);
|
|
|
assign div_wait_nxt = ({4{dec_swl_div_inst_d & swl_dec_divbusy_e &
|
assign div_wait_nxt = ({4{dec_swl_div_inst_d & swl_dec_divbusy_e &
|
fcl_dtu_inst_vld_d & ~iferr_d}} &
|
fcl_dtu_inst_vld_d & ~iferr_d}} &
|
thr_d & ~rt_st_thr_e | div_done | // set
|
thr_d & ~rt_st_thr_e | div_done | // set
|
div_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
div_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
(~trp_no_retr);
|
(~trp_no_retr);
|
|
|
dffr #(4) dw_ff(.din (div_wait_nxt[3:0]),
|
dffr_s #(4) dw_ff(.din (div_wait_nxt[3:0]),
|
.q (div_wait[3:0]),
|
.q (div_wait[3:0]),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign div_wait_any = (|div_wait[3:0]);
|
assign div_wait_any = (|div_wait[3:0]);
|
|
|
assign fp_wait_nxt = ({4{dec_swl_allfp_d & // swl_dec_fp_enable_d &
|
assign fp_wait_nxt = ({4{dec_swl_allfp_d & // swl_dec_fp_enable_d &
|
fcl_dtu_inst_vld_d & fpbusy_local_e &
|
fcl_dtu_inst_vld_d & fpbusy_local_e &
|
~iferr_d}} &
|
~iferr_d}} &
|
thr_d & ~rt_st_thr_d & ~rt_st_thr_e |
|
thr_d & ~rt_st_thr_d & ~rt_st_thr_e |
|
fp_done | // set
|
fp_done | // set
|
fp_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
fp_wait & ~retr_thr_wakeup & ~killed_uniop_done_e) &
|
(~trp_no_retr);
|
(~trp_no_retr);
|
|
|
dffr #(4) fw_ff(.din (fp_wait_nxt[3:0]),
|
dffr_s #(4) fw_ff(.din (fp_wait_nxt[3:0]),
|
.q (fp_wait[3:0]),
|
.q (fp_wait[3:0]),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se(se), .si(), .so());
|
.se(se), `SIMPLY_RISC_SCANIN, .so());
|
assign fp_wait_any = (|fp_wait[3:0]);
|
assign fp_wait_any = (|fp_wait[3:0]);
|
|
|
// wake up waiting threads when the unit is no longer busy
|
// wake up waiting threads when the unit is no longer busy
|
// need to qual with trp_no_retr since trp can occur at the same
|
// need to qual with trp_no_retr since trp can occur at the same
|
// time as unit becoming unbusy.
|
// time as unit becoming unbusy.
|
| Line 1661... |
Line 1487... |
//--------------------------
|
//--------------------------
|
// Store buffer flow control
|
// Store buffer flow control
|
//--------------------------
|
//--------------------------
|
// store pipe
|
// store pipe
|
assign st_inst_qual_d = dec_swl_st_inst_d & fcl_dtu_inst_vld_d;
|
assign st_inst_qual_d = dec_swl_st_inst_d & fcl_dtu_inst_vld_d;
|
dff ste_ff(.din (st_inst_qual_d),
|
dff_s ste_ff(.din (st_inst_qual_d),
|
.q (st_inst_e),
|
.q (st_inst_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
assign st_inst_qual_e = st_inst_e & ~dtu_inst_anull_e;
|
assign st_inst_qual_e = st_inst_e & ~dtu_inst_anull_e;
|
|
|
dff stm_ff(.din (st_inst_qual_e),
|
dff_s stm_ff(.din (st_inst_qual_e),
|
.q (st_inst_m),
|
.q (st_inst_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff stg_ff(.din (st_inst_m),
|
dff_s stg_ff(.din (st_inst_m),
|
.q (st_inst_g),
|
.q (st_inst_g),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign st_inst_qual_g = st_inst_g & ifu_tlu_inst_vld_w;
|
// assign st_inst_qual_g = st_inst_g & ifu_tlu_inst_vld_w;
|
// dff stw2_ff(.din (st_inst_qual_g),
|
// dff stw2_ff(.din (st_inst_qual_g),
|
// .q (st_inst_w2),
|
// .q (st_inst_w2),
|
// .clk (clk),
|
// .clk (clk),
|
// .se (se), .si(), .so());
|
// .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// determine which of the above thread is to the D thread
|
// determine which of the above thread is to the D thread
|
assign same_thr_de = (thr_d[0] & thr_e[0] |
|
assign same_thr_de = (thr_d[0] & thr_e[0] |
|
thr_d[1] & thr_e[1] |
|
thr_d[1] & thr_e[1] |
|
thr_d[2] & thr_e[2] |
|
thr_d[2] & thr_e[2] |
|
| Line 1714... |
Line 1540... |
assign pipe_st_e = same_thr_fe & st_inst_e;
|
assign pipe_st_e = same_thr_fe & st_inst_e;
|
assign pipe_st_m = same_thr_fm & st_inst_m;
|
assign pipe_st_m = same_thr_fm & st_inst_m;
|
assign pipe_st_g = same_thr_fg & st_inst_g;
|
assign pipe_st_g = same_thr_fg & st_inst_g;
|
assign pipe_st_d = same_thr_fd & st_inst_qual_d;
|
assign pipe_st_d = same_thr_fd & st_inst_qual_d;
|
|
|
dff #(1) pste_ff(.din (pipe_st_d),
|
dff_s #(1) pste_ff(.din (pipe_st_d),
|
.q (st_thisthr_e),
|
.q (st_thisthr_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// count the number of stores in the pipe to this thread (0-4)
|
// count the number of stores in the pipe to this thread (0-4)
|
assign pipe_st_cnt_ge1 = pipe_st_e | pipe_st_m | pipe_st_g;
|
assign pipe_st_cnt_ge1 = pipe_st_e | pipe_st_m | pipe_st_g;
|
// pipe_st_w2;
|
// pipe_st_w2;
|
|
|
| Line 1741... |
Line 1567... |
// pipe_st_m & pipe_st_g & pipe_st_w2);
|
// pipe_st_m & pipe_st_g & pipe_st_w2);
|
|
|
// assign pipe_st_cnt_eq4 = pipe_st_e & pipe_st_m & pipe_st_g &
|
// assign pipe_st_cnt_eq4 = pipe_st_e & pipe_st_m & pipe_st_g &
|
// pipe_st_w2;
|
// pipe_st_w2;
|
|
|
dff #(3) pstc_reg(.din ({pipe_st_cnt_ge1,
|
dff_s #(3) pstc_reg(.din ({pipe_st_cnt_ge1,
|
pipe_st_cnt_ge2,
|
pipe_st_cnt_ge2,
|
pipe_st_cnt_ge3}),
|
pipe_st_cnt_ge3}),
|
.q ({dst_cnt_ge1,
|
.q ({dst_cnt_ge1,
|
dst_cnt_ge2,
|
dst_cnt_ge2,
|
dst_cnt_ge3}),
|
dst_cnt_ge3}),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// get the number of taken store buffer entries to this thread
|
// get the number of taken store buffer entries to this thread
|
mux4ds #(4) stbcnt_mux(.dout (stbcnt_s),
|
mux4ds #(4) stbcnt_mux(.dout (stbcnt_s),
|
.in0 (lsu_ifu_stbcnt0),
|
.in0 (lsu_ifu_stbcnt0),
|
.in1 (lsu_ifu_stbcnt1),
|
.in1 (lsu_ifu_stbcnt1),
|
| Line 1760... |
Line 1586... |
.sel0 (thr_f[0]),
|
.sel0 (thr_f[0]),
|
.sel1 (thr_f[1]),
|
.sel1 (thr_f[1]),
|
.sel2 (thr_f[2]),
|
.sel2 (thr_f[2]),
|
.sel3 (thr_f[3]));
|
.sel3 (thr_f[3]));
|
|
|
dff #(4) stbd_reg(.din (stbcnt_s),
|
dff_s #(4) stbd_reg(.din (stbcnt_s),
|
.q (stbcnt_d),
|
.q (stbcnt_d),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign all_dst_ge1 = dst_cnt_ge1 | st_thisthr_e;
|
assign all_dst_ge1 = dst_cnt_ge1 | st_thisthr_e;
|
assign all_dst_ge2 = dst_cnt_ge1 & st_thisthr_e | dst_cnt_ge2;
|
assign all_dst_ge2 = dst_cnt_ge1 & st_thisthr_e | dst_cnt_ge2;
|
assign all_dst_ge3 = dst_cnt_ge2 & st_thisthr_e | dst_cnt_ge3;
|
assign all_dst_ge3 = dst_cnt_ge2 & st_thisthr_e | dst_cnt_ge3;
|
assign all_dst_eq4 = dst_cnt_ge3 & st_thisthr_e;
|
assign all_dst_eq4 = dst_cnt_ge3 & st_thisthr_e;
|
| Line 1783... |
Line 1609... |
|
|
assign stb_stall = {4{switch_store_d}} & thr_d;
|
assign stb_stall = {4{switch_store_d}} & thr_d;
|
assign stb_blocked = {lsu_ifu_stbcnt3[3], lsu_ifu_stbcnt2[3],
|
assign stb_blocked = {lsu_ifu_stbcnt3[3], lsu_ifu_stbcnt2[3],
|
lsu_ifu_stbcnt1[3], lsu_ifu_stbcnt0[3]};
|
lsu_ifu_stbcnt1[3], lsu_ifu_stbcnt0[3]};
|
|
|
dff #(4) stbb_reg(.din (stb_blocked),
|
dff_s #(4) stbb_reg(.din (stb_blocked),
|
.q (stb_blocked_d1),
|
.q (stb_blocked_d1),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// retract this thread if taken entries + stores in pipe >= 9
|
// retract this thread if taken entries + stores in pipe >= 9
|
assign retract_store_d = dec_swl_st_inst_d & fcl_dtu_inst_vld_d &
|
assign retract_store_d = dec_swl_st_inst_d & fcl_dtu_inst_vld_d &
|
(stbcnt_d[3] | // 8
|
(stbcnt_d[3] | // 8
|
stbcnt_d[2] & stbcnt_d[1] & stbcnt_d[0] & all_dst_ge1 | // 7 + 1
|
stbcnt_d[2] & stbcnt_d[1] & stbcnt_d[0] & all_dst_ge1 | // 7 + 1
|
| Line 1801... |
Line 1627... |
// the next cycle
|
// the next cycle
|
assign retract_st_next_d = (retract_store_d | retract_iferr_d) &
|
assign retract_st_next_d = (retract_store_d | retract_iferr_d) &
|
~(same_thr_dg & rollback_g) &
|
~(same_thr_dg & rollback_g) &
|
~trp_noretr_d;
|
~trp_noretr_d;
|
|
|
dff #(1) retr_se(.din (retract_st_next_d),
|
dff_s #(1) retr_se(.din (retract_st_next_d),
|
.q (retract_store_e),
|
.q (retract_store_e),
|
.clk (clk), .se (se), .si(), .so());
|
.clk (clk), .se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// clear wmo if you set it already
|
// clear wmo if you set it already
|
assign clear_wmo_e = retract_store_e & (swc_d & same_thr_de | swc_e);
|
assign clear_wmo_e = retract_store_e & (swc_d & same_thr_de | swc_e);
|
// assign clear_wmo_e = retract_store_e;
|
// assign clear_wmo_e = retract_store_e;
|
|
|
| Line 1822... |
Line 1648... |
|
|
// assign stb_wait_nxt = ({4{switch_store_d}} & thr_d & ~rb_thr_w | // set
|
// assign stb_wait_nxt = ({4{switch_store_d}} & thr_d & ~rb_thr_w | // set
|
// wm_stbwait & ~stb_retry) & ~trp_no_retr;
|
// wm_stbwait & ~stb_retry) & ~trp_no_retr;
|
|
|
assign stb_wait_nxt = ({4{switch_store_d}} & thr_d | // set
|
assign stb_wait_nxt = ({4{switch_store_d}} & thr_d | // set
|
wm_stbwait & ~stb_retry|wait_state & ~wbm_spc_resume);
|
wm_stbwait & ~stb_retry);
|
|
|
dffr #(4) stbw_reg(.din (stb_wait_nxt),
|
dffr_s #(4) stbw_reg(.din (stb_wait_nxt),
|
.q (wm_stbwait),
|
.q (wm_stbwait),
|
.clk (clk),
|
.clk (clk),
|
.rst (dtu_reset),
|
.rst (dtu_reset),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// count to 4 and retry
|
// count to 4 and retry
|
dff stbrete_ff(.din (switch_store_d),
|
dff_s stbrete_ff(.din (switch_store_d),
|
.q (sw_st_e),
|
.q (sw_st_e),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff stbretm_ff(.din (sw_st_e),
|
dff_s stbretm_ff(.din (sw_st_e),
|
.q (sw_st_m),
|
.q (sw_st_m),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff stbretg_ff(.din (sw_st_m),
|
dff_s stbretg_ff(.din (sw_st_m),
|
.q (sw_st_g),
|
.q (sw_st_g),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
dff stbretw2_ff(.din (sw_st_g),
|
dff_s stbretw2_ff(.din (sw_st_g),
|
.q (sw_st_w2),
|
.q (sw_st_w2),
|
.clk (clk),
|
.clk (clk),
|
.se (se), .si(), .so());
|
.se (se), `SIMPLY_RISC_SCANIN, .so());
|
// assign stb_retry = {4{sw_st_w2}} & st_thr_w2 & ~stb_blocked;
|
// assign stb_retry = {4{sw_st_w2}} & st_thr_w2 & ~stb_blocked;
|
|
|
assign st_in_pipe = ({4{sw_st_e}} & thr_e |
|
assign st_in_pipe = ({4{sw_st_e}} & thr_e |
|
{4{sw_st_m}} & thr_m |
|
{4{sw_st_m}} & thr_m |
|
{4{sw_st_g}} & thr_w |
|
{4{sw_st_g}} & thr_w |
|
| Line 1862... |
Line 1688... |
|
|
|
|
//
|
//
|
// Quad Stores
|
// Quad Stores
|
//
|
//
|
dff #(1) stde_ff(.din (dec_swl_std_inst_d),
|
dff_s #(1) stde_ff(.din (dec_swl_std_inst_d),
|
.q (std_inst_e),
|
.q (std_inst_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign stq_inst_e = std_inst_e & lsu_ifu_quad_asi_e & fcl_dtu_inst_vld_e;
|
// assign stq_inst_e = std_inst_e & lsu_ifu_quad_asi_e & fcl_dtu_inst_vld_e;
|
assign std_done_e = std_inst_e & ~lsu_ifu_quad_asi_e & fcl_dtu_inst_vld_e;
|
assign std_done_e = std_inst_e & ~lsu_ifu_quad_asi_e & fcl_dtu_inst_vld_e;
|
dff #(1) stdm_ff(.din (std_done_e),
|
dff_s #(1) stdm_ff(.din (std_done_e),
|
.q (std_done_m),
|
.q (std_done_m),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// dff #(1) stqm_ff(.din (stq_inst_e),
|
// dff #(1) stqm_ff(.din (stq_inst_e),
|
// .q (stq_inst_m),
|
// .q (stq_inst_m),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// dff #(1) stqw_ff(.din (stq_inst_m),
|
// dff #(1) stqw_ff(.din (stq_inst_m),
|
// .q (stq_inst_w),
|
// .q (stq_inst_w),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
// dff #(1) stqw2_ff(.din (stq_inst_w),
|
// dff #(1) stqw2_ff(.din (stq_inst_w),
|
// .q (stq_inst_w2),
|
// .q (stq_inst_w2),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// assign stq_in_pipe = ({4{stq_inst_m}} & thr_m |
|
// assign stq_in_pipe = ({4{stq_inst_m}} & thr_m |
|
// {4{stq_inst_w}} & thr_w |
|
// {4{stq_inst_w}} & thr_w |
|
// {4{stq_inst_w2}} & st_thr_w2);
|
// {4{stq_inst_w2}} & st_thr_w2);
|
|
|
| Line 1893... |
Line 1719... |
// stq_wait & stq_busy;
|
// stq_wait & stq_busy;
|
|
|
// dffr #(4) stqwait_reg(.din (stq_wait_next),
|
// dffr #(4) stqwait_reg(.din (stq_wait_next),
|
// .q (stq_wait),
|
// .q (stq_wait),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
// .clk (clk), .se(se), .si(), .so());
|
// .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
//
|
//
|
// assign stq_done_thr = stq_wait & ~stq_busy | thr_m & {4{std_done_m}};
|
// assign stq_done_thr = stq_wait & ~stq_busy | thr_m & {4{std_done_m}};
|
|
|
|
|
//-----------------------------
|
//-----------------------------
|
// FPRS
|
// FPRS
|
//-----------------------------
|
//-----------------------------
|
dff #(3) wrtd_w_reg(.din (thr_config_in_m[2:0]),
|
dff_s #(3) wrtd_w_reg(.din (thr_config_in_m[2:0]),
|
.q (thr_config_in_w[2:0]),
|
.q (thr_config_in_w[2:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
dff #(3) wrtd_w2_reg(.din (thr_config_in_w[2:0]),
|
dff_s #(3) wrtd_w2_reg(.din (thr_config_in_w[2:0]),
|
.q (thr_config_in_w2[2:0]),
|
.q (thr_config_in_w2[2:0]),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fprs_wrt_data = thr_config_in_w2;
|
assign fprs_wrt_data = thr_config_in_w2;
|
mux3ds #(3) fprs_mx0(.dout (fprs0_nxt),
|
mux3ds #(3) fprs_mx0(.dout (fprs0_nxt),
|
.in0 (fprs_wrt_data),
|
.in0 (fprs_wrt_data),
|
.in1 (fprs0),
|
.in1 (fprs0),
|
| Line 1941... |
Line 1767... |
.sel1 (fprs_sel_old[3]),
|
.sel1 (fprs_sel_old[3]),
|
.sel2 (fprs_sel_set[3]));
|
.sel2 (fprs_sel_set[3]));
|
|
|
// make resettable for now. Eventually change to non-reset
|
// make resettable for now. Eventually change to non-reset
|
// Done
|
// Done
|
dff #(3) t0_fprs(.din (fprs0_nxt),
|
dff_s #(3) t0_fprs(.din (fprs0_nxt),
|
.q (fprs0),
|
.q (fprs0),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) t1_fprs(.din (fprs1_nxt),
|
dff_s #(3) t1_fprs(.din (fprs1_nxt),
|
.q (fprs1),
|
.q (fprs1),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) t2_fprs(.din (fprs2_nxt),
|
dff_s #(3) t2_fprs(.din (fprs2_nxt),
|
.q (fprs2),
|
.q (fprs2),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
dff #(3) t3_fprs(.din (fprs3_nxt),
|
dff_s #(3) t3_fprs(.din (fprs3_nxt),
|
.q (fprs3),
|
.q (fprs3),
|
// .rst (dtu_reset),
|
// .rst (dtu_reset),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign fprs_en_s = {fprs3[2],fprs2[2],fprs1[2],fprs0[2]};
|
assign fprs_en_s = {fprs3[2],fprs2[2],fprs1[2],fprs0[2]};
|
assign fpen_vec_s = (tlu_ifu_pstate_pef & fprs_en_s & thr_f);
|
assign fpen_vec_s = (tlu_ifu_pstate_pef & fprs_en_s & thr_f);
|
assign fpen_s = (|fpen_vec_s[3:0]);
|
assign fpen_s = (|fpen_vec_s[3:0]);
|
dff #(1) fpend_ff(.din (fpen_s),
|
dff_s #(1) fpend_ff(.din (fpen_s),
|
.q (swl_dec_fp_enable_d),
|
.q (swl_dec_fp_enable_d),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
// unprotected since synopsys does not use one hot mux
|
// unprotected since synopsys does not use one hot mux
|
mux4ds #(3) curr_fprs_mx(.dout (fprs_d),
|
mux4ds #(3) curr_fprs_mx(.dout (fprs_d),
|
.in0 (fprs0),
|
.in0 (fprs0),
|
.in1 (fprs1),
|
.in1 (fprs1),
|
| Line 1976... |
Line 1802... |
.sel0 (thr_d[0]),
|
.sel0 (thr_d[0]),
|
.sel1 (thr_d[1]),
|
.sel1 (thr_d[1]),
|
.sel2 (thr_d[2]),
|
.sel2 (thr_d[2]),
|
.sel3 (thr_d[3]));
|
.sel3 (thr_d[3]));
|
|
|
dff #(3) fprse_reg(.din (fprs_d),
|
dff_s #(3) fprse_reg(.din (fprs_d),
|
.q (fprs_e),
|
.q (fprs_e),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign new_fprs[1] = dec_swl_frf_upper_d | fprs_d[1];
|
assign new_fprs[1] = dec_swl_frf_upper_d | fprs_d[1];
|
assign new_fprs[0] = dec_swl_frf_lower_d | fprs_d[0];
|
assign new_fprs[0] = dec_swl_frf_lower_d | fprs_d[0];
|
|
|
// writes to fprs are done by software
|
// writes to fprs are done by software
|
assign wrt_fprs_w = ifu_tlu_inst_vld_w & dec_swl_wrtfprs_w &
|
assign wrt_fprs_w = ifu_tlu_inst_vld_w & dec_swl_wrtfprs_w &
|
~flush_all_w;
|
~flush_all_w;
|
|
|
dff #(1) fpwr_ff(.din (wrt_fprs_w),
|
dff_s #(1) fpwr_ff(.din (wrt_fprs_w),
|
.q (wrt_fprs_w2),
|
.q (wrt_fprs_w2),
|
.clk (clk), .se(se), .si(), .so());
|
.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
|
|
|
assign sel_wrt = st_thr_w2 & {4{wrt_fprs_w2}};
|
assign sel_wrt = st_thr_w2 & {4{wrt_fprs_w2}};
|
assign fprs_sel_set = thr_d & {4{dec_swl_fpop_d & swl_dec_fp_enable_d &
|
assign fprs_sel_set = thr_d & {4{dec_swl_fpop_d & swl_dec_fp_enable_d &
|
fcl_dtu_inst_vld_d}};
|
fcl_dtu_inst_vld_d}};
|
assign fprs_sel_wrt = ~fprs_sel_set & sel_wrt;
|
assign fprs_sel_wrt = ~fprs_sel_set & sel_wrt;
|
