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// You should have received a copy of the GNU General Public
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
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// ========== Copyright Header End ============================================
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// ========== Copyright Header End ============================================
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`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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//FPGA_SYN enables all FPGA related modifications
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK_EN
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`define FPGA_SYN_CLK_DFF
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`endif
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module sparc_mul_dp(
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module sparc_mul_dp(
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ecl_mul_rs1_data,
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ecl_mul_rs1_data,
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ecl_mul_rs2_data,
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ecl_mul_rs2_data,
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spu_mul_op1_data,
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spu_mul_op1_data,
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Line 148... |
.areg (areg),
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.areg (areg),
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.accreg (acc_reg[135:129]),
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.accreg (acc_reg[135:129]),
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.x2 (x2),
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.x2 (x2),
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.out (mout),
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.out (mout),
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.rclk (clk),
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.rclk (clk),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so (),
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.so (),
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.se (se),
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.se (se),
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.mul_rst_l (rst_l),
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.mul_rst_l (rst_l),
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.mul_step (1'b1)
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.mul_step (1'b1)
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);
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);
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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///// ACCUM register and right shift muxes
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///// ACCUM register and right shift muxes
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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dff dffshf (.din (acc_reg_shf),
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dff_s dffshf (.din (acc_reg_shf),
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.clk (clk),
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.clk (clk),
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.q (acc_reg_shf2),
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.q (acc_reg_shf2),
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.se (se),
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.se (se),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so ()
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.so ()
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);
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);
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assign acc_reg_in = acc_reg_shf ? {64'b0,acc_reg[135:64]}
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assign acc_reg_in = acc_reg_shf ? {64'b0,acc_reg[135:64]}
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: mout ;
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: mout ;
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assign mul_data_out = acc_reg_shf2 ? acc_reg[63:0]
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assign mul_data_out = acc_reg_shf2 ? acc_reg[63:0]
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: mout[63:0] ;
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: mout[63:0] ;
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`ifdef FPGA_SYN_CLK_DFF
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dffre #(136) accum (.din (acc_reg_in),
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dffre_s #(136) accum (.din (acc_reg_in),
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.rst (acc_reg_rst),
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.rst (acc_reg_rst),
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.en (acc_reg_enb | acc_reg_rst), .clk(clk), //manually fixed
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.en (acc_reg_enb | acc_reg_rst), .clk(clk), //manually fixed
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.q (acc_reg),
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.q (acc_reg),
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.se (se),
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.se (se),
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.si (),
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`SIMPLY_RISC_SCANIN,
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.so ()
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.so ()
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);
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);
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`else
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dffr_s #(136) accum (.din (acc_reg_in),
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.rst (acc_reg_rst),
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.clk (clk_enb1),
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.q (acc_reg),
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.se (se),
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`SIMPLY_RISC_SCANIN,
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.so ()
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);
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`endif
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`ifdef FPGA_SYN_CLK_EN
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`else
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clken_buf ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(acc_reg_enb | acc_reg_rst)), .tmb_l(~se));
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`endif
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assign bypreg = byp_imm ? mout[63:0]
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assign bypreg = byp_imm ? mout[63:0]
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: acc_reg[63:0] ;
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: acc_reg[63:0] ;
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