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[/] [s6soc/] [trunk/] [Makefile] - Diff between revs 34 and 50

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Line 37... Line 37...
##############################################################################//
##############################################################################//
##
##
##
##
.PHONY: all
.PHONY: all
all:    datestamp archive rtl sw
all:    datestamp archive rtl sw
# BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
 
BENCH :=
BENCH :=
 
SIM := `find sim -name Makefile` `find sim -name "*.cpp"` `find sim -name "*.h"`
RTL   := `find rtl -name "*.v"` `find rtl -name Makefile`
RTL   := `find rtl -name "*.v"` `find rtl -name Makefile`
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
NOTES := `find doc -name "*.txt"` `find doc -name "*.html"` `ls *.txt`
SW    := `find sw -name "*.cpp"` `find sw -name "*.h"`  \
SW    := `find sw -name "*.cpp"` `find sw -name "*.h"`  \
        `find sw -name "*.c"` `find sw -name "*.sh"`    \
        `find sw -name "*.c"` `find sw -name "*.sh"`    \
        `find sw -name "*.pl"` `find sw -name Makefile`
        `find sw -name "*.pl"` `find sw -name Makefile`
# PROJ  := xilinx/xula.prj xilinx/xula.xise xilinx/xula.xst     \
 
#       xilinx/xula.ut xilinx/Makefile
 
PROJ    :=
PROJ    :=
BIN     := `find xilinx -name "*.bit"`
BIN     := `find xilinx -name "*.bit"`
CONSTRAINTS := cmod.ucf
CONSTRAINTS := cmod.ucf
YYMMDD  := `date +%Y%m%d`
YYMMDD  := `date +%Y%m%d`
 
 
.PHONY: datestamp
.PHONY: datestamp
datestamp:
datestamp:
        @bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
        @bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm -f 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
        @bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi'
        @bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi'
 
 
.PHONY: rtl
.PHONY: rtl
rtl:
rtl:
        @make --no-print-directory -C rtl
        @make --no-print-directory -C rtl
Line 68... Line 66...
 
 
.PHONY: doc
.PHONY: doc
doc:
doc:
        @make --no-print-directory -C doc
        @make --no-print-directory -C doc
 
 
.PHONY: bench
.PHONY: sim
bench: rtl
bench: rtl
        @make --no-print-directory -C bench/cpp
        @make --no-print-directory -C sim/verilator
 
 
 
.PHONY: list-archive-rtl
 
list-archive-rtl:
 
        echo $(RTL)
 
 
 
.PHONY: list-archive-sw
 
list-archive-sw:
 
        echo $(SW)
 
 
 
.PHONY: list-archive-bin
 
list-archive-bin:
 
        echo $(BIN)
 
 
 
.PHONY: list-archive-notes
 
list-archive-notes:
 
        echo $(NOTES)
 
 
 
.PHONY: list-archive-proj
 
list-archive-proj:
 
        echo $(PROJ)
 
 
 
.PHONY: list-archive
 
list-archive: list-archive-sw list-archive-rtl list-archive-notes list-archive-proj list-archive-bin
 
 
.PHONY: archive
.PHONY: archive
archive:
archive:
        tar --transform s,^,$(YYMMDD)-s6/, -chjf $(YYMMDD)-s6.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
        tar --transform s,^,$(YYMMDD)-s6/, -chjf $(YYMMDD)-s6.tjz $(SIM) $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
 
 
# .PHONY: bit
# .PHONY: bit
# bit:
# bit:
#       make --no-print-directory -C xilinx toplevel.bit
#       make --no-print-directory -C xilinx toplevel.bit
 
 
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# but I can't speak to whether it would be useful or not.
# but I can't speak to whether it would be useful or not.
 
 
xload:
xload:
        djtgcfg init -d CmodS6
        djtgcfg init -d CmodS6
        djtgcfg prog -d CmodS6 -i 0 -f xilinx/toplevel.bit
        djtgcfg prog -d CmodS6 -i 0 -f xilinx/toplevel.bit
 
 
 
# Fload really depends upon axload, but we'll ignore that here.
 
fload:
 
        sw/host/zipload xilinx/toplevel.bit sw/zipos/doorbell

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