| Line 37... |
Line 37... |
##############################################################################//
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##############################################################################//
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##
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##
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##
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##
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.PHONY: all
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.PHONY: all
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all: datestamp archive rtl sw
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all: datestamp archive rtl sw
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# BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
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BENCH :=
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BENCH :=
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SIM := `find sim -name Makefile` `find sim -name "*.cpp"` `find sim -name "*.h"`
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RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
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RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
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NOTES := `find . -name "*.txt"` `find . -name "*.html"`
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NOTES := `find doc -name "*.txt"` `find doc -name "*.html"` `ls *.txt`
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SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
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SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
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`find sw -name "*.c"` `find sw -name "*.sh"` \
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`find sw -name "*.c"` `find sw -name "*.sh"` \
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`find sw -name "*.pl"` `find sw -name Makefile`
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`find sw -name "*.pl"` `find sw -name Makefile`
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# PROJ := xilinx/xula.prj xilinx/xula.xise xilinx/xula.xst \
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# xilinx/xula.ut xilinx/Makefile
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PROJ :=
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PROJ :=
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BIN := `find xilinx -name "*.bit"`
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BIN := `find xilinx -name "*.bit"`
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CONSTRAINTS := cmod.ucf
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CONSTRAINTS := cmod.ucf
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YYMMDD := `date +%Y%m%d`
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YYMMDD := `date +%Y%m%d`
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|
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.PHONY: datestamp
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.PHONY: datestamp
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datestamp:
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datestamp:
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@bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
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@bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm -f 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
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@bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi'
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@bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi'
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|
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.PHONY: rtl
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.PHONY: rtl
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rtl:
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rtl:
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@make --no-print-directory -C rtl
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@make --no-print-directory -C rtl
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| Line 68... |
Line 66... |
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.PHONY: doc
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.PHONY: doc
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doc:
|
doc:
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@make --no-print-directory -C doc
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@make --no-print-directory -C doc
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|
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.PHONY: bench
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.PHONY: sim
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bench: rtl
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bench: rtl
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@make --no-print-directory -C bench/cpp
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@make --no-print-directory -C sim/verilator
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|
|
|
.PHONY: list-archive-rtl
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list-archive-rtl:
|
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echo $(RTL)
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|
|
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.PHONY: list-archive-sw
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list-archive-sw:
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echo $(SW)
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|
|
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.PHONY: list-archive-bin
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list-archive-bin:
|
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echo $(BIN)
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|
|
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.PHONY: list-archive-notes
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list-archive-notes:
|
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echo $(NOTES)
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|
|
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.PHONY: list-archive-proj
|
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list-archive-proj:
|
|
echo $(PROJ)
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|
|
|
.PHONY: list-archive
|
|
list-archive: list-archive-sw list-archive-rtl list-archive-notes list-archive-proj list-archive-bin
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|
|
.PHONY: archive
|
.PHONY: archive
|
archive:
|
archive:
|
tar --transform s,^,$(YYMMDD)-s6/, -chjf $(YYMMDD)-s6.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
|
tar --transform s,^,$(YYMMDD)-s6/, -chjf $(YYMMDD)-s6.tjz $(SIM) $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
|
|
|
# .PHONY: bit
|
# .PHONY: bit
|
# bit:
|
# bit:
|
# make --no-print-directory -C xilinx toplevel.bit
|
# make --no-print-directory -C xilinx toplevel.bit
|
|
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| Line 91... |
Line 112... |
# but I can't speak to whether it would be useful or not.
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# but I can't speak to whether it would be useful or not.
|
|
|
xload:
|
xload:
|
djtgcfg init -d CmodS6
|
djtgcfg init -d CmodS6
|
djtgcfg prog -d CmodS6 -i 0 -f xilinx/toplevel.bit
|
djtgcfg prog -d CmodS6 -i 0 -f xilinx/toplevel.bit
|
|
|
|
# Fload really depends upon axload, but we'll ignore that here.
|
|
fload:
|
|
sw/host/zipload xilinx/toplevel.bit sw/zipos/doorbell
|
