URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

[/] [s6soc/] [trunk/] [bench/] [cpp/] [Makefile] - Diff between revs 2 and 10

Rev 2	Rev 10
Line 34...	Line 34...
`#`	`#`
`all: zip_sim`	`all: zip_sim`

`CXX := g++`	`CXX := g++`
`FLAGS := -Wall -Og -g`	`FLAGS := -Wall -Og -g`
`ZASM := ../../sw/zasm`	`SWHOST := ../../sw/host`
`RTLD := ../../rtl`	`RTLD := ../../rtl`
`INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I$(ZASM)`	`INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include \`
	`-I$(SWHOST)`
`SOURCES := zip_sim.cpp twoc.cpp qspiflashsim.cpp uartsim.cpp`	`SOURCES := zip_sim.cpp twoc.cpp qspiflashsim.cpp uartsim.cpp`
`VLIB := /usr/share/verilator/include/verilated.cpp`	`VLIB := /usr/share/verilator/include/verilated.cpp`
`RAWLIB := $(VLIB) $(RTLD)/obj_dir/Vbusmaster__ALL.a`	`RAWLIB := $(VLIB) $(RTLD)/obj_dir/Vbusmaster__ALL.a`
`LIBS := $(RAWLIB)`	`LIBS := $(RAWLIB) -lelf`
`TESTF := $(ZASM)/z.out`	`TESTF := $(ZASM)/z.out`
`DHRYSTONEF := ../asm/zipdhry.z`	`DHRYSTONEF := ../asm/zipdhry.z`

`zip_sim: $(SOURCES) $(RAWLIB) testb.h`	`zip_sim: $(SOURCES) $(RAWLIB) testb.h`
`$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@`	`$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@`