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\documentclass{gqtekspec}

\documentclass{gqtekspec}

\usepackage{import}

\usepackage{import}

\usepackage{bytefield}

\usepackage{bytefield}

\project{CMod S6 SoC}

\project{CMod S6 SoC}

\title{Specification}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\author{Dan Gisselquist, Ph.D.}

You should have received a copy of the GNU General Public License along

You should have received a copy of the GNU General Public License along

with this program.  If not, see \texttt{http://www.gnu.org/licenses/} for a copy.

with this program.  If not, see \texttt{http://www.gnu.org/licenses/} for a copy.

\end{license}

\end{license}

\begin{revisionhistory}

\begin{revisionhistory}

0.3 & 5/23/2016 & Gisselquist & Draft for comment, includes ZipOS and PMod

0.3 & 5/23/2016 & Gisselquist & Draft for comment, includes ZipOS and PMod

                pin mapping\\\hline

                pin mapping\\\hline

0.2 & 5/14/2016 & Gisselquist & Updated Draft, still not complete \\\hline

0.2 & 5/14/2016 & Gisselquist & Updated Draft, still not complete \\\hline

0.1 & 4/22/2016 & Gisselquist & First Draft \\\hline

0.1 & 4/22/2016 & Gisselquist & First Draft \\\hline

\end{revisionhistory}

\end{revisionhistory}

reloaded with the primary configuration file which will contain an image of

reloaded with the primary configuration file which will contain an image of

the CPU.  The CPU will then begin following the instructions found in flash

the CPU.  The CPU will then begin following the instructions found in flash

memory.

memory.

\chapter{Software}

\chapter{Software}

This chapter provides an overview of the software that is available to support

This chapter provides an overview of the software that is available to support

the S6~SoC.  This includes not only the RTL, the Makefiles, and the software

the S6~SoC.  This includes not only the RTL, the Makefiles, and the software

that will run on the Zip~CPU within the S6~SoC, but also the support software

that will run on the Zip~CPU within the S6~SoC, but also the support software

necessary for communicating with the S6~SoC in its alternate configuration.

necessary for communicating with the S6~SoC in its alternate configuration.

        ``Hello, world!''  This program sends the string, ``Hello, world!''

        ``Hello, world!''  This program sends the string, ``Hello, world!''

        over the UART connection once per second.  It is a very valuable

        over the UART connection once per second.  It is a very valuable

        program because, if you can get this program running, you know you have

        program because, if you can get this program running, you know you have

        a lot of things working and working correctly.  For example, running

        a lot of things working and working correctly.  For example, running

        this program means you can run the {\tt zip-gcc} compiler, load

        this program means you can run the {\tt zip-gcc} compiler, load

        the primary configuration, and read from the UART port.  It also means

        the primary configuration, and read from the UART port.  It also means

        that you must have the UART port properly configured and wired to your

        that you must have the UART port properly configured and wired to your

        CMod board.

        CMod board.

\item {\tt doorbell}: This annoying program verifies the functionality of the

\item {\tt doorbell}: This annoying program verifies the functionality of the

        audio device by playing a doorbell sound to the audio port.  It will

        audio device by playing a doorbell sound to the audio port.  It will

        In a similar fashion, if the timeout is negative, then any pending

        In a similar fashion, if the timeout is negative, then any pending

        timeout is cleared.

        timeout is cleared.

\item {\tt void post(unsigned event\_mask)}

\item {\tt void post(unsigned event\_mask)}

        reader, need the ability of being able to post events to any listener

        reader, need the ability of being able to post events to any listener

        within the O/S.  The POST system call allows them to POST events in

        within the O/S.  The POST system call allows them to POST events in

        this manner.

        this manner.

        Were the ZipOS to be closer to a secure O/S, it might restrict what

        Were the ZipOS to be closer to a secure O/S, it might restrict what

There are several address regions on the S6~SoC, as shown in

There are several address regions on the S6~SoC, as shown in

Tbl.~\ref{tbl:memregions}.

Tbl.~\ref{tbl:memregions}.

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline

\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline

\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline

\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline

\end{tabular}

\end{tabular}

\caption{Address Regions}\label{tbl:memregions}

\caption{Address Regions}\label{tbl:memregions}

\end{center}\end{table}

\end{center}\end{table}

In general, the address regions that are made up of RAM or flash act like

In general, the address regions that are made up of RAM or flash act like

memory.  The RAM can be read and written, and the flash acts like read only

memory.  The RAM can be read and written, and the flash acts like read only

memory.\footnote{The Flash can be written, but only by an external command

memory.\footnote{The Flash can be written, but only by an external command

This isn't quite true with the other address regions.  Accessing the I/O

This isn't quite true with the other address regions.  Accessing the I/O

region, while it will act like a memory, it may also have side-effects.  For

region, while it will act like a memory, it may also have side-effects.  For

example, reading from the debugging scope device's data port will read a word

example, reading from the debugging scope device's data port will read a word

from the scope's buffer and advance the buffer pointer.  (More on that later.)

from the scope's buffer and advance the buffer pointer.  (More on that later.)

Finally, to keep the address decoder simple, many of these addresses are

Finally, to keep the address decoder simple, many of these addresses are

multiply mapped.  Hence you may find the I/O peripherals mapped throughout the

multiply mapped.  Hence you may find the I/O peripherals mapped throughout the

overmapped.  This overmapping was a resource minimization feature, to get the

overmapped.  This overmapping was a resource minimization feature, to get the

\section{Peripheral I/O Control}

\section{Peripheral I/O Control}

Tbl.~\ref{tbl:ioregs}

Tbl.~\ref{tbl:ioregs}

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}\begin{reglist}

\begin{center}\begin{reglist}

\end{reglist}

\end{reglist}

\caption{I/O Peripheral Registers}\label{tbl:ioregs}

\caption{I/O Peripheral Registers}\label{tbl:ioregs}

\end{center}\end{table}

\end{center}\end{table}

shows the addresses of various I/O peripherals included as part of the SoC.

shows the addresses of various I/O peripherals included as part of the SoC.

We'll walk through each of these peripherals in turn, describing how they work.

We'll walk through each of these peripherals in turn, describing how they work.

Interrupts are acknowledged in a fashion similar to enabling interrupts.  By

Interrupts are acknowledged in a fashion similar to enabling interrupts.  By

writing a `1' to the active bit mask, the interrupt will be acknowledged and

writing a `1' to the active bit mask, the interrupt will be acknowledged and

reset, whereas writing a `0' leaves the interrupt untouched.  In this fashion,

reset, whereas writing a `0' leaves the interrupt untouched.  In this fashion,

as individual interrupts are handled, a `1' may be written to this bottom mask

as individual interrupts are handled, a `1' may be written to this bottom mask

\subsection{Last Bus Error Address}

\subsection{Last Bus Error Address}

The Bus Error peripheral simply records the address of the last bus error,

The Bus Error peripheral simply records the address of the last bus error,

and sets an interrupt upon receiving a bus error.  (The interrupt itself

and sets an interrupt upon receiving a bus error.  (The interrupt itself

is kind of useless ...) The address can be useful when debugging.  While the

is kind of useless ...) The address can be useful when debugging.  While the

Another use for this is upon any reboot, it is possible to read the address

Another use for this is upon any reboot, it is possible to read the address

of the last bus error and perhaps learn something of what caused the CPU to

of the last bus error and perhaps learn something of what caused the CPU to

restart.

restart.

\subsection{ZipTimer}

\subsection{ZipTimer}

running will cause that new value to automatically load into the timer and

running will cause that new value to automatically load into the timer and

start counting from there.  Writing a zero to the timer disables the timer, and

start counting from there.  Writing a zero to the timer disables the timer, and

causes it to stop.

causes it to stop.

load it's last set value upon reaching zero and interrupting the CPU.  This

load it's last set value upon reaching zero and interrupting the CPU.  This

effectively turns it into an interrupt timer if desired.  To set this feature,

effectively turns it into an interrupt timer if desired.  To set this feature,

write to the timer the number of clock ticks before an interrupt, but also set

write to the timer the number of clock ticks before an interrupt, but also set

the high order bit.  In this fashion, writing a {\tt 0x8001387f} will interrupt

the high order bit.  In this fashion, writing a {\tt 0x8001387f} will interrupt

the CPU every millisecond, starting one millisecond after the write takes place

the CPU every millisecond, starting one millisecond after the write takes place

(assuming an 80~MHz system clock).\footnote{Note that, since the timer spends

(assuming an 80~MHz system clock).\footnote{Note that, since the timer spends

a cycle at zero, setting it for a 80,000 cycle period requires setting the

a cycle at zero, setting it for a 80,000 cycle period requires setting the

timer value to one less than 80,000.}

timer value to one less than 80,000.}

1~ms, the ZipOS examines every task for a potential task swap every millisecond.

1~ms, the ZipOS examines every task for a potential task swap every millisecond.

Of course, if the various tasks are running from Flash at 52~clocks per

Of course, if the various tasks are running from Flash at 52~clocks per

instruction, this means that as few as 1,538~instructions may be executed

instruction, this means that as few as 1,538~instructions may be executed

between timer interrupts, but this can be tuned if necessary for better

between timer interrupts, but this can be tuned if necessary for better

performance.

performance.

\subsection{UART Data Register}

\subsection{UART Data Register}

Moving on to the UART \ldots although the UART module itself

Moving on to the UART \ldots although the UART module itself

within the S6~SoC is highly configurable, as built

within the S6~SoC is highly configurable, as built

the UART can only handle 9600~Baud, 8--data bits, no parity, and one stop bit.

the UART can only handle 9600~Baud, 8--data bits, no parity, and one stop bit.

reading from the port has a real--time requirement associated with it: the

reading from the port has a real--time requirement associated with it: the

data buffer must be emptied before the next value is read.

data buffer must be emptied before the next value is read.

Attempts to read from this port will either return an 8--bit data value from

Attempts to read from this port will either return an 8--bit data value from

the port, or if no values are available it will return an {\tt 0x0100}

the port, or if no values are available it will return an {\tt 0x0100}

indicating that fact.  In general, reading from the UART port involves first

indicating that fact.  In general, reading from the UART port involves first

waiting for the interrupt to be ready, second reading from the port itself,

waiting for the interrupt to be ready, second reading from the port itself,

and then third immediately  clearing the interrupt.  (The interrupt cannot

and then third immediately  clearing the interrupt.  (The interrupt cannot

be cleared while data is waiting.)  Writing to the UART port is done in a

be cleared while data is waiting.)  Writing to the UART port is done in a

similar fashion.  First, wait until the UART transmit interrupt is asserted

similar fashion.  First, wait until the UART transmit interrupt is asserted

transmit interrupt prior to writing to the port will have no effect.  Likewise,

transmit interrupt prior to writing to the port will have no effect.  Likewise,

clearing the transmit interrupt after the byte has been written will have no

clearing the transmit interrupt after the byte has been written will have no

affect either.

affect either.

\section{Debugging Scope}

\section{Debugging Scope}

register.  It needs to be internally wired to 32--wires, internal to the

register.  It needs to be internally wired to 32--wires, internal to the

S6~SoC, that will be of interest when debugging.  For further details on how

S6~SoC, that will be of interest when debugging.  For further details on how

to configure and use this scope, please see the {\tt WBSCOPE} project on

to configure and use this scope, please see the {\tt WBSCOPE} project on

OpenCores.

OpenCores.

\section{On-Chip Block RAM}

\section{On-Chip Block RAM}

The block RAM is the fastest memory available to the processor.  It is also

The block RAM is the fastest memory available to the processor.  It is also

the {\em only} writeable memory available to the processor.  Hence all

the {\em only} writeable memory available to the processor.  Hence all

non-constant program data {\em must} be placed into block RAM.  The Zip~CPU

non-constant program data {\em must} be placed into block RAM.  The Zip~CPU

and the third section for any program and data.  These regions are shown in

and the third section for any program and data.  These regions are shown in

Tbl.~\ref{tbl:flash-addresses}.

Tbl.~\ref{tbl:flash-addresses}.

\begin{table}[htbp]

\begin{table}[htbp]

\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline

\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline

\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline

\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline

\end{tabular}

\end{tabular}

\caption{Flash Address Regions}\label{tbl:flash-addresses}

\caption{Flash Address Regions}\label{tbl:flash-addresses}

\end{center}\end{table}

\end{center}\end{table}

The host program {\tt zipload} can be used to load a Zip~CPU program and

The host program {\tt zipload} can be used to load a Zip~CPU program and

configuration files into this address space.  To use it, first load the

configuration files into this address space.  To use it, first load the