`timescale 10ns / 100ps
|
`timescale 10ns / 100ps
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Filename: alttop.v
|
// Filename: alttop.v
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//
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose: This is an alternate toplevel configuration for the CMod S6
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// Purpose: This is an alternate toplevel configuration for the CMod S6
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// project. Basically, the CMod S6 has so little logic within
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// project. Basically, the CMod S6 has so little logic within
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// it, that there's no logic available for in situ reprogramming. This
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// it, that there's no logic available for in situ reprogramming. This
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// toplevel file serves that purpose: It provides full configuration
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// toplevel file serves that purpose: It provides full configuration
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// access, via the UART port, for the flash (read and write), and full
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// access, via the UART port, for the flash (read and write), and full
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// test level access for all of the devices on the board. What it
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// test level access for all of the devices on the board. What it
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// doesn't have, however, is the ZipCPU. (I had to give up something to
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// doesn't have, however, is the ZipCPU. (I had to give up something to
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// get the logic back for this purpose!)
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// get the logic back for this purpose!)
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module alttop(i_clk_8mhz,
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module alttop(i_clk_8mhz,
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o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
|
o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
|
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_uart, o_uart, i_uart_cts, o_uart_rts,
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i_uart, o_uart, o_uart_cts, i_uart_rts,
|
i_kp_row, o_kp_col,
|
i_kp_row, o_kp_col,
|
i_gpio, o_gpio,
|
i_gpio, o_gpio,
|
io_scl, io_sda,
|
io_scl, io_sda,
|
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, io_depp_data,
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i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, io_depp_data,
|
o_depp_wait
|
o_depp_wait
|
);
|
);
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input i_clk_8mhz;
|
input i_clk_8mhz;
|
//
|
//
|
// Quad SPI Flash
|
// Quad SPI Flash
|
output wire o_qspi_cs_n;
|
output wire o_qspi_cs_n;
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output wire o_qspi_sck;
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output wire o_qspi_sck;
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inout wire [3:0] io_qspi_dat;
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inout wire [3:0] io_qspi_dat;
|
//
|
//
|
// General purpose I/O
|
// General purpose I/O
|
input [1:0] i_btn;
|
input [1:0] i_btn;
|
output wire [3:0] o_led;
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output wire [3:0] o_led;
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output wire o_pwm, o_pwm_shutdown_n, o_pwm_gain;
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output wire o_pwm, o_pwm_shutdown_n, o_pwm_gain;
|
//
|
//
|
// and our serial port
|
// and our serial port
|
input i_uart;
|
input i_uart;
|
output wire o_uart;
|
output wire o_uart;
|
// and it's associated control wires
|
// and it's associated control wires
|
input i_uart_cts;
|
output wire o_uart_cts;
|
output wire o_uart_rts;
|
input i_uart_rts;
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// Our keypad
|
// Our keypad
|
input [3:0] i_kp_row;
|
input [3:0] i_kp_row;
|
output wire [3:0] o_kp_col;
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output wire [3:0] o_kp_col;
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// and our GPIO
|
// and our GPIO
|
input [15:2] i_gpio;
|
input [15:2] i_gpio;
|
output wire [15:2] o_gpio;
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output wire [15:2] o_gpio;
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// and our I2C port
|
// and our I2C port
|
inout io_scl, io_sda;
|
inout io_scl, io_sda;
|
// Finally, the DEPP interface ... if so enabled
|
// Finally, the DEPP interface ... if so enabled
|
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
|
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
|
inout [7:0] io_depp_data;
|
inout [7:0] io_depp_data;
|
output wire o_depp_wait;
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output wire o_depp_wait;
|
|
|
//
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//
|
// Clock management
|
// Clock management
|
//
|
//
|
// Generate a usable clock for the rest of the board to run at.
|
// Generate a usable clock for the rest of the board to run at.
|
//
|
//
|
wire ck_zero_0, clk_s;
|
wire ck_zero_0, clk_s;
|
|
|
// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
|
// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
|
// Clock period = 12.5 ns
|
// Clock period = 12.5 ns
|
DCM_SP #(
|
DCM_SP #(
|
.CLKDV_DIVIDE(2.0),
|
.CLKDV_DIVIDE(2.0),
|
.CLKFX_DIVIDE(2), // Here's the divide by two
|
.CLKFX_DIVIDE(2), // Here's the divide by two
|
.CLKFX_MULTIPLY(20), // and here's the multiply by 20
|
.CLKFX_MULTIPLY(20), // and here's the multiply by 20
|
.CLKIN_DIVIDE_BY_2("FALSE"),
|
.CLKIN_DIVIDE_BY_2("FALSE"),
|
.CLKIN_PERIOD(125.0),
|
.CLKIN_PERIOD(125.0),
|
.CLKOUT_PHASE_SHIFT("NONE"),
|
.CLKOUT_PHASE_SHIFT("NONE"),
|
.CLK_FEEDBACK("1X"),
|
.CLK_FEEDBACK("1X"),
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
|
.DLL_FREQUENCY_MODE("LOW"),
|
.DLL_FREQUENCY_MODE("LOW"),
|
.DUTY_CYCLE_CORRECTION("TRUE"),
|
.DUTY_CYCLE_CORRECTION("TRUE"),
|
.PHASE_SHIFT(0),
|
.PHASE_SHIFT(0),
|
.STARTUP_WAIT("TRUE")
|
.STARTUP_WAIT("TRUE")
|
) u0( .CLKIN(i_clk_8mhz),
|
) u0( .CLKIN(i_clk_8mhz),
|
.CLK0(ck_zero_0),
|
.CLK0(ck_zero_0),
|
.CLKFB(ck_zero_0),
|
.CLKFB(ck_zero_0),
|
.CLKFX(clk_s),
|
.CLKFX(clk_s),
|
.PSEN(1'b0),
|
.PSEN(1'b0),
|
.RST(1'b0));
|
.RST(1'b0));
|
|
|
//
|
//
|
// The UART serial interface
|
// The UART serial interface
|
//
|
//
|
// Perhaps this should be part of our simulation model as well.
|
// Perhaps this should be part of our simulation model as well.
|
// For historical reasons, internal to Gisselquist Technology,
|
// For historical reasons, internal to Gisselquist Technology,
|
// this has remained separate from the simulation, allowing the
|
// this has remained separate from the simulation, allowing the
|
// simulation to bypass whether or not these two functions work.
|
// simulation to bypass whether or not these two functions work.
|
//
|
//
|
wire rx_stb, tx_stb;
|
wire rx_stb, tx_stb;
|
wire [7:0] rx_data, tx_data;
|
wire [7:0] rx_data, tx_data;
|
wire tx_busy;
|
wire tx_busy;
|
wire [29:0] uart_setup;
|
wire [29:0] uart_setup;
|
|
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
|
assign tx_break = 1'b0;
|
assign tx_break = 1'b0;
|
rxuart rcvuart(clk_s, 1'b0, uart_setup,
|
rxuart rcvuart(clk_s, 1'b0, uart_setup,
|
i_uart, rx_stb, rx_data,
|
i_uart, rx_stb, rx_data,
|
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
|
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
|
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
|
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
|
o_uart, i_uart_cts, tx_busy);
|
o_uart, tx_busy);
|
|
|
|
|
//
|
//
|
// ALT-BUSMASTER
|
// ALT-BUSMASTER
|
//
|
//
|
// Busmaster is so named because it contains the wishbone
|
// Busmaster is so named because it contains the wishbone
|
// interconnect that all of the internal devices are hung off of.
|
// interconnect that all of the internal devices are hung off of.
|
// To reconfigure this device for another purpose, usually
|
// To reconfigure this device for another purpose, usually
|
// the busmaster module (i.e. the interconnect) is all that needs
|
// the busmaster module (i.e. the interconnect) is all that needs
|
// to be changed: either to add more devices, or to remove them.
|
// to be changed: either to add more devices, or to remove them.
|
//
|
//
|
// This is an alternate version of the busmaster interface,
|
// This is an alternate version of the busmaster interface,
|
// offering no ZipCPU and access to reprogramming via the flash.
|
// offering no ZipCPU and access to reprogramming via the flash.
|
//
|
//
|
wire [3:0] qspi_dat;
|
wire [3:0] qspi_dat;
|
wire [1:0] qspi_bmod;
|
wire [1:0] qspi_bmod;
|
wire [15:0] w_gpio;
|
wire [15:0] w_gpio;
|
wire [7:0] w_depp_data;
|
wire [7:0] w_depp_data;
|
|
|
`ifndef BYPASS_LOGIC
|
`ifndef BYPASS_LOGIC
|
altbusmaster slavedbus(clk_s, reset_s,
|
altbusmaster slavedbus(clk_s, 1'b0,
|
// External ... bus control (if enabled)
|
// External ... bus control (if enabled)
|
// DEPP I/O Control
|
// DEPP I/O Control
|
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
|
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
|
io_depp_data, w_depp_data, o_depp_wait,
|
io_depp_data, w_depp_data, o_depp_wait,
|
// External UART interface
|
// External UART interface
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
|
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts,
|
// SPI/SD-card flash
|
// SPI/SD-card flash
|
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
|
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
|
// Board lights and switches
|
// Board lights and switches
|
i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
|
i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
|
// Keypad connections
|
// Keypad connections
|
i_kp_row, o_kp_col,
|
i_kp_row, o_kp_col,
|
// UART control
|
// UART control
|
uart_setup,
|
uart_setup,
|
// GPIO lines
|
// GPIO lines
|
{ i_gpio, io_scl, io_sda }, w_gpio
|
{ i_gpio, io_scl, io_sda }, w_gpio
|
);
|
);
|
|
assign o_uart_cts = (w_uart_cts)&&(i_uart_rts);
|
|
|
//
|
//
|
// Quad SPI support
|
// Quad SPI support
|
//
|
//
|
// Supporting a Quad SPI port requires knowing which direction the
|
// Supporting a Quad SPI port requires knowing which direction the
|
// wires are going at each instant, whether the device is in full
|
// wires are going at each instant, whether the device is in full
|
// Quad mode in, full quad mode out, or simply the normal SPI
|
// Quad mode in, full quad mode out, or simply the normal SPI
|
// port with one wire in and one wire out. This utilizes our
|
// port with one wire in and one wire out. This utilizes our
|
// control wires (qspi_bmod) to set the output lines appropriately.
|
// control wires (qspi_bmod) to set the output lines appropriately.
|
//
|
//
|
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
|
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
|
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
|
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
|
|
|
`else
|
`else
|
reg [26:0] r_counter;
|
reg [26:0] r_counter;
|
always @(posedge clk_s)
|
always @(posedge clk_s)
|
r_counter <= r_counter+1;
|
r_counter <= r_counter+1;
|
assign o_led[0] = r_counter[26];
|
assign o_led[0] = r_counter[26];
|
assign o_led[1] = r_counter[25];
|
assign o_led[1] = r_counter[25];
|
assign o_led[2] = r_counter[24];
|
assign o_led[2] = r_counter[24];
|
assign o_led[3] = r_counter[23];
|
assign o_led[3] = r_counter[23];
|
// assign o_led[0] = 1'b1;
|
// assign o_led[0] = 1'b1;
|
// assign o_led[1] = 1'b0;
|
// assign o_led[1] = 1'b0;
|
// assign o_led[2] = 1'b1;
|
// assign o_led[2] = 1'b1;
|
// assign o_led[3] = 1'b0;
|
// assign o_led[3] = 1'b0;
|
|
|
assign w_gpio = 16'h3;
|
assign w_gpio = 16'h3;
|
assign o_pwm = 1'b0;
|
assign o_pwm = 1'b0;
|
assign o_pwm_shutdown_n = 1'b0;
|
assign o_pwm_shutdown_n = 1'b0;
|
assign o_pwm_gain = 1'b0;
|
assign o_pwm_gain = 1'b0;
|
|
|
assign o_depp_wait = (~i_depp_astb_n);
|
assign o_depp_wait = (~i_depp_astb_n);
|
assign w_depp_data = 8'h00;
|
assign w_depp_data = 8'h00;
|
assign io_qspi_dat = 4'bzzzz;
|
assign io_qspi_dat = 4'bzzzz;
|
assign o_qspi_cs_n = 1'b1;
|
assign o_qspi_cs_n = 1'b1;
|
assign o_qspi_sck = 1'b1;
|
assign o_qspi_sck = 1'b1;
|
|
|
assign uart_setup = 30'h080002b6;
|
assign uart_setup = 30'h080002b6;
|
|
|
assign o_uart_rts = 1'b1;
|
assign o_uart_cts = 1'b1;
|
`endif
|
`endif
|
//
|
//
|
// I2C support
|
// I2C support
|
//
|
//
|
// Supporting I2C requires a couple quick adjustments to our
|
// Supporting I2C requires a couple quick adjustments to our
|
// GPIO lines. Specifically, we'll allow that when the output
|
// GPIO lines. Specifically, we'll allow that when the output
|
// (i.e. w_gpio) pins are high, then the I2C lines float. They
|
// (i.e. w_gpio) pins are high, then the I2C lines float. They
|
// will be (need to be) pulled up by a resistor in order to
|
// will be (need to be) pulled up by a resistor in order to
|
// match the I2C protocol, but this change makes them look/act
|
// match the I2C protocol, but this change makes them look/act
|
// more like GPIO pins.
|
// more like GPIO pins.
|
//
|
//
|
assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
|
assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
|
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
|
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
|
assign o_gpio[15:2] = w_gpio[15:2];
|
assign o_gpio[15:2] = w_gpio[15:2];
|
|
|
//
|
//
|
// DEPP return data support
|
// DEPP return data support
|
//
|
//
|
assign io_depp_data = (~i_depp_write_n)? 8'bzzzz_zzzz : w_depp_data;
|
assign io_depp_data = (~i_depp_write_n)? 8'bzzzz_zzzz : w_depp_data;
|
|
|
endmodule
|
endmodule
|
|
|
