| Line 58... |
Line 58... |
// UART control
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// UART control
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o_uart_setup,
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o_uart_setup,
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// GPIO lines
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// GPIO lines
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i_gpio, o_gpio);
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i_gpio, o_gpio);
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parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
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CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
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ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output reg o_tx_stb;
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output reg o_tx_stb;
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| Line 220... |
Line 220... |
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
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/*
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/*
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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assign many_sel =((wb_cyc)&&(wb_stb)&&(
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{3'h0, io_sel}
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{3'h0, io_sel}
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+{3'h0, flctl_sel}
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+{3'h0, flctl_sel}
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// +{3'h0, scop_sel}
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+{3'h0, scop_sel}
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+{3'h0, cfg_sel}
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+{3'h0, cfg_sel}
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+{3'h0, rtc_sel}
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+{3'h0, mem_sel}
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+{3'h0, mem_sel}
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+{3'h0, flash_sel} > 1));
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+{3'h0, flash_sel} > 1));
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*/
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*/
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assign many_sel = 1'b0;
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assign many_sel = 1'b0;
|
|
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| Line 262... |
Line 263... |
initial bus_err_addr = 0; // `DATESTAMP;
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initial bus_err_addr = 0; // `DATESTAMP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
|
|
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
|
wire [31:0] timer_a, timer_b;
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wire [31:0] timer_a, timer_b;
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ziptimer #(32,20)
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
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ziptimer #(32,31)
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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tmra_int);
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tmra_int);
|
ziptimer #(32,20)
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ziptimer #(32,31)
|
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
tmrb_int);
|
tmrb_int);
|
|
|
| Line 387... |
Line 388... |
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wire flash_cs_n, flash_sck, flash_mosi;
|
|
wbqspiflash #(24) flashmem(i_clk,
|
wbqspiflash #(24) flashmem(i_clk,
|
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[(24-3):0], wb_data,
|
wb_addr[(24-3):0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_interrupt);
|
flash_interrupt);
|
|
|
