| Line 37... |
Line 37... |
//
|
//
|
//
|
//
|
`include "builddate.v"
|
`include "builddate.v"
|
//
|
//
|
`define INCLUDE_ZIPPY
|
`define INCLUDE_ZIPPY
|
`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
|
`define IMPLEMENT_ONCHIP_RAM
|
`ifndef VERILATOR
|
`ifndef VERILATOR
|
`define FANCY_ICAP_ACCESS
|
`define FANCY_ICAP_ACCESS
|
`endif
|
`endif
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
|
// `define COMPRESSED_SCOPE
|
|
`define INCLUDE_SECOND_TIMER
|
|
`define INCLUDE_CPU_RESET_LOGIC
|
// `define INCLUDE_RTC // About 90 LUTs
|
// `define INCLUDE_RTC // About 90 LUTs
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
o_uart_cts,
|
o_uart_cts,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
| Line 120... |
Line 123... |
//
|
//
|
//
|
//
|
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
|
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
|
wire [(ZA-1):0] w_zip_addr;
|
wire [(ZA-1):0] w_zip_addr;
|
wire [(BAW-1):0] zip_addr;
|
wire [(BAW-1):0] zip_addr;
|
wire [31:0] zip_data;
|
wire [31:0] zip_data, zip_scope_data;
|
// and then coming from devices
|
// and then coming from devices
|
wire zip_ack, zip_stall, zip_err;
|
wire zip_ack, zip_stall, zip_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire [(BAW-1):0] dwb_addr;
|
wire [(BAW-1):0] dwb_addr;
|
wire [31:0] dwb_odata;
|
wire [31:0] dwb_odata;
|
| Line 142... |
Line 145... |
// the program separately. So, instead, let's place our RESET address at the
|
// the program separately. So, instead, let's place our RESET address at the
|
// second flash erase block. That way, we can change our program code found
|
// second flash erase block. That way, we can change our program code found
|
// in the flash without needing to change our FPGA load and vice versa.
|
// in the flash without needing to change our FPGA load and vice versa.
|
//
|
//
|
// 23'h404000
|
// 23'h404000
|
|
wire cpu_reset;
|
|
`ifdef INCLUDE_CPU_RESET_LOGIC
|
|
reg btn_reset, x_button, r_button;
|
|
initial btn_reset = 1'b0;
|
|
initial x_button = 1'b0;
|
|
initial r_button = 1'b0;
|
|
always @(posedge i_clk)
|
|
begin
|
|
x_button <= i_btn[1];
|
|
r_button <= x_button;
|
|
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
|
|
end
|
|
assign cpu_reset = btn_reset;
|
|
`else
|
|
assign cpu_reset = 1'b0;
|
|
`endif
|
|
|
zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
|
zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
|
thecpu(i_clk, 1'b0,
|
thecpu(i_clk, btn_reset, // 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
|
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
|
wb_ack, wb_stall, wb_idata, wb_err,
|
wb_ack, wb_stall, wb_idata, wb_err,
|
w_interrupt, zip_cpu_int,
|
w_interrupt, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface -- not really used
|
1'b0, 1'b0,1'b0, 1'b0, 32'h00,
|
1'b0, 1'b0,1'b0, 1'b0, 32'h00,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data);
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
|
|
zip_scope_data);
|
generate
|
generate
|
if (ZA < BAW)
|
if (ZA < BAW)
|
assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
|
assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
|
else
|
else
|
assign wb_addr = w_zip_addr;
|
assign wb_addr = w_zip_addr;
|
| Line 217... |
Line 238... |
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
/*
|
/*
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&
|
|
((io_addr==6'h0)
|
|
||((~io_addr[5])&&(|wb_addr[22:14])))
|
|
);
|
|
*/
|
|
/*
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
{3'h0, io_sel}
|
{3'h0, io_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, cfg_sel}
|
| Line 268... |
Line 295... |
|
|
wire [31:0] timer_a, timer_b;
|
wire [31:0] timer_a, timer_b;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
ziptimer #(32,31)
|
ziptimer #(32,31)
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
|
`ifdef INCLUDE_SECOND_TIMER
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
|
`else
|
|
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
|
|
`endif
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
tmra_int);
|
tmra_int);
|
|
`ifdef INCLUDE_SECOND_TIMER
|
ziptimer #(32,31)
|
ziptimer #(32,31)
|
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
tmrb_int);
|
tmrb_int);
|
|
`else
|
|
// assign timer_b = 32'h000;
|
|
assign timer_b = timer_a;
|
|
assign tmrb_int = 1'b0;
|
|
`endif
|
|
|
wire [31:0] rtc_data;
|
wire [31:0] rtc_data;
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
wire rtcd_ack, rtcd_stall, ppd;
|
wire rtcd_ack, rtcd_stall, ppd;
|
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
|
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
|
| Line 329... |
Line 366... |
pwm_int);
|
pwm_int);
|
|
|
//
|
//
|
// Special Purpose I/O: Keypad, button, LED status and control
|
// Special Purpose I/O: Keypad, button, LED status and control
|
//
|
//
|
|
wire [3:0] w_led;
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
|
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, o_led,
|
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
|
keypad_int, button_int);
|
keypad_int, button_int);
|
|
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
|
|
|
//
|
//
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// direction for an I2C link at the toplevel.v design)
|
// direction for an I2C link at the toplevel.v design)
|
//
|
//
|
| Line 445... |
Line 484... |
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cfg_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
`ifdef DBG_SCOPE
|
`ifdef DBG_SCOPE
|
wire scop_cfg_trigger;
|
wire scop_cfg_trigger;
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
|
// wire scop_trigger = scop_cfg_trigger;
|
|
wire scop_trigger = (zip_cpu_int) || (cpu_reset);
|
|
`ifdef COMPRESSED_SCOPE
|
|
wbscopc #(5'ha)
|
|
`else
|
|
wbscope #(5'ha)
|
|
`endif
|
|
wbcfgscope(i_clk, 1'b1, scop_trigger,
|
|
// cfg_scope,
|
|
zip_scope_data[30:0],
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
|
wb_we, wb_addr[0], wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
scop_cfg_interrupt);
|
scop_cfg_interrupt);
|
