| Line 45... |
Line 45... |
`endif
|
`endif
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
// `define COMPRESSED_SCOPE
|
// `define COMPRESSED_SCOPE
|
`define INCLUDE_SECOND_TIMER
|
`define INCLUDE_SECOND_TIMER
|
`define INCLUDE_CPU_RESET_LOGIC
|
`define SECOND_TIMER_IS_WATCHDOG
|
// `define INCLUDE_RTC // About 90 LUTs
|
// `define INCLUDE_RTC // About 90 LUTs
|
|
// `define FULL_BUSERR_CALCULATION
|
|
`define INCLUDE_CPU_RESET_LOGIC
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
o_uart_cts,
|
o_uart_cts,
|
// The SPI Flash lines
|
// The SPI Flash lines
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
| Line 145... |
Line 147... |
// the program separately. So, instead, let's place our RESET address at the
|
// the program separately. So, instead, let's place our RESET address at the
|
// second flash erase block. That way, we can change our program code found
|
// second flash erase block. That way, we can change our program code found
|
// in the flash without needing to change our FPGA load and vice versa.
|
// in the flash without needing to change our FPGA load and vice versa.
|
//
|
//
|
// 23'h404000
|
// 23'h404000
|
wire cpu_reset;
|
wire cpu_reset, tmrb_int;
|
`ifdef INCLUDE_CPU_RESET_LOGIC
|
`ifdef INCLUDE_CPU_RESET_LOGIC
|
reg btn_reset, x_button, r_button;
|
reg btn_reset, x_button, r_button;
|
initial btn_reset = 1'b0;
|
initial btn_reset = 1'b0;
|
initial x_button = 1'b0;
|
initial x_button = 1'b0;
|
initial r_button = 1'b0;
|
initial r_button = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
x_button <= i_btn[1];
|
x_button <= i_btn[1];
|
r_button <= x_button;
|
r_button <= x_button;
|
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
|
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
|
|
`else
|
|
btn_reset <= ((r_button)&&(zip_cpu_int));
|
|
`endif
|
end
|
end
|
assign cpu_reset = btn_reset;
|
assign cpu_reset = btn_reset;
|
`else
|
`else
|
assign cpu_reset = 1'b0;
|
assign cpu_reset = 1'b0;
|
`endif
|
`endif
|
| Line 181... |
Line 187... |
assign wb_addr = w_zip_addr;
|
assign wb_addr = w_zip_addr;
|
endgenerate
|
endgenerate
|
|
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
|
rtc_sel, none_sel, many_sel;
|
rtc_sel, none_sel, many_sel;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
|
wire rtc_ack, rtc_stall;
|
wire rtc_ack, rtc_stall;
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
assign rtc_stall = 1'b0;
|
assign rtc_stall = 1'b0;
|
`endif
|
`endif
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
| Line 226... |
Line 232... |
|
|
// Addresses ...
|
// Addresses ...
|
// 0000 xxxx configuration/control registers
|
// 0000 xxxx configuration/control registers
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
|
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
|
|
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
|
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
|
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
|
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
|
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
|
// zip_sel is not on the bus at this point
|
// zip_sel is not on the bus at this point
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
|
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
|
`endif
|
`endif
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
`ifdef FULL_BUSERR_CALCULATION
|
/*
|
assign none_sel =((wb_cyc)&&(wb_stb)&&
|
assign none_sel =((wb_cyc)&&(wb_stb)&&
|
((io_addr==6'h0)
|
((io_addr==6'h0)
|
||((~io_addr[5])&&(|wb_addr[22:14]))
|
||((~io_addr[5])&&(|wb_addr[22:14])))
|
||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
|
);
|
);
|
*/
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
/*
|
{3'h0, io_sel}
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
+{3'h0, flctl_sel}
|
{3'h0, io_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, flctl_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, scop_sel}
|
+{3'h0, rtc_sel}
|
+{3'h0, cfg_sel}
|
+{3'h0, mem_sel}
|
+{3'h0, rtc_sel}
|
+{3'h0, flash_sel} > 1));
|
+{3'h0, mem_sel}
|
|
+{3'h0, flash_sel} > 1));
|
|
*/
|
|
assign many_sel = 1'b0;
|
|
|
|
wire many_ack;
|
|
assign many_ack =((wb_cyc)&&(
|
assign many_ack =((wb_cyc)&&(
|
{3'h0, io_ack}
|
{3'h0, io_ack}
|
+{3'h0, scop_ack}
|
+{3'h0, scop_ack}
|
+{3'h0, cfg_ack}
|
+{3'h0, cfg_ack}
|
`ifdef INCLUDE_RTC
|
`ifdef INCLUDE_RTC
|
+{3'h0, rtc_ack}
|
+{3'h0, rtc_ack}
|
`endif
|
`endif
|
+{3'h0, mem_ack}
|
+{3'h0, mem_ack}
|
+{3'h0, flash_ack} > 1));
|
+{3'h0, flash_ack} > 1));
|
|
`else
|
wire flash_interrupt, scop_interrupt, tmra_int, tmrb_int,
|
assign many_ack = 1'b0;
|
|
assign many_sel = 1'b0;
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
|
|
`endif
|
|
wire flash_interrupt, scop_interrupt, tmra_int,
|
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
|
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
|
|
|
|
|
//
|
//
|
//
|
//
|
//
|
//
|
reg rx_rdy;
|
reg rx_rdy;
|
wire [10:0] int_vector;
|
wire [10:0] int_vector;
|
assign int_vector = { gpio_int, pwm_int, keypad_int,
|
assign int_vector = {
|
|
gpio_int, pwm_int, keypad_int,
|
(~o_tx_stb), rx_rdy,
|
(~o_tx_stb), rx_rdy,
|
tmrb_int, tmra_int,
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
|
1'b0,
|
|
`else
|
|
tmrb_int,
|
|
`endif
|
|
tmra_int,
|
rtc_interrupt, scop_interrupt,
|
rtc_interrupt, scop_interrupt,
|
wb_err, button_int };
|
wb_err, button_int };
|
|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
| Line 293... |
Line 304... |
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= wb_addr;
|
bus_err_addr <= wb_addr;
|
|
|
wire [31:0] timer_a, timer_b;
|
wire [31:0] timer_a, timer_b;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
ziptimer #(32,31)
|
ziptimer #(32,31,1)
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
`ifdef INCLUDE_SECOND_TIMER
|
`ifdef INCLUDE_SECOND_TIMER
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
`else
|
`else
|
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
|
`endif
|
`endif
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
tmra_int);
|
tmra_int);
|
`ifdef INCLUDE_SECOND_TIMER
|
`ifdef INCLUDE_SECOND_TIMER
|
ziptimer #(32,31)
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
|
ziptimer #(32,31,0)
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
tmrb_int);
|
tmrb_int);
|
`else
|
`else
|
|
ziptimer #(32,31,1)
|
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
|
tmrb_int);
|
|
`endif
|
|
`else
|
// assign timer_b = 32'h000;
|
// assign timer_b = 32'h000;
|
assign timer_b = timer_a;
|
assign timer_b = timer_a;
|
assign tmrb_int = 1'b0;
|
assign tmrb_int = 1'b0;
|
`endif
|
`endif
|
|
|
