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[/] [s6soc/] [trunk/] [rtl/] [busmaster.v] - Diff between revs 2 and 4

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//
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    busmaster.v
// Filename:    busmaster.v
//
//
// Project:     FPGA library development (S6 development board)
// Project:     CMod S6 System on a Chip, ZipCPU demonstration project
//
//
// Purpose:
// Purpose:
//
//
// Creator:     Dan Gisselquist
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
// Copyright:   2015
////////////////////////////////////////////////////////////////////////////////
 
//
 
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
 
//
 
// This program is free software (firmware): you can redistribute it and/or
 
// modify it under the terms of  the GNU General Public License as published
 
// by the Free Software Foundation, either version 3 of the License, or (at
 
// your option) any later version.
 
//
 
// This program is distributed in the hope that it will be useful, but WITHOUT
 
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 
// for more details.
 
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
 
// License:     GPL, v3, as defined and found on www.gnu.org,
 
//              http://www.gnu.org/licenses/gpl.html
 
//
 
//
 
////////////////////////////////////////////////////////////////////////////////
 
//
//
//
//
//
`include "builddate.v"
`include "builddate.v"
//
//
`define NO_ZIP_WBU_DELAY
 
`define INCLUDE_ZIPPY
`define INCLUDE_ZIPPY
`define IMPLEMENT_ONCHIP_RAM
`define IMPLEMENT_ONCHIP_RAM    // 2804 w/o after synthesis
`ifndef VERILATOR
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`define FANCY_ICAP_ACCESS
`endif
`endif
`define FLASH_ACCESS
`define FLASH_ACCESS
`define CFG_SCOPE
// `define      CFG_SCOPE       // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC     // 2017 slice LUTs w/o, 2108 with (!!!)
`define INCLUDE_RTC     // About 90 LUTs
module  busmaster(i_clk, i_rst,
module  busmaster(i_clk, i_rst,
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
 
                        o_uart_rts,
                // The SPI Flash lines
                // The SPI Flash lines
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
                o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
                // The board I/O
                // The board I/O
                i_btn, o_led, o_pwm, o_pwm_aux,
                i_btn, o_led, o_pwm, o_pwm_aux,
                // Keypad connections
                // Keypad connections
Line 43... Line 67...
        input                   i_rx_stb;
        input                   i_rx_stb;
        input           [7:0]    i_rx_data;
        input           [7:0]    i_rx_data;
        output  reg             o_tx_stb;
        output  reg             o_tx_stb;
        output  reg     [7:0]    o_tx_data;
        output  reg     [7:0]    o_tx_data;
        input                   i_tx_busy;
        input                   i_tx_busy;
 
        output  wire            o_uart_rts;
        // SPI flash control
        // SPI flash control
        output  wire            o_qspi_cs_n, o_qspi_sck;
        output  wire            o_qspi_cs_n, o_qspi_sck;
        output  wire    [3:0]    o_qspi_dat;
        output  wire    [3:0]    o_qspi_dat;
        input           [3:0]    i_qspi_dat;
        input           [3:0]    i_qspi_dat;
        output  wire    [1:0]    o_qspi_mod;
        output  wire    [1:0]    o_qspi_mod;
Line 142... Line 167...
        wire    rtc_ack, rtc_stall;
        wire    rtc_ack, rtc_stall;
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
        assign  rtc_stall = 1'b0;
        assign  rtc_stall = 1'b0;
`endif
`endif
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
        reg     io_ack, uart_ack;
        reg     io_ack;
 
 
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
        wire    [31:0]   flash_data, scop_data, cfg_data, mem_data, pwm_data,
                        spio_data, gpio_data, uart_data;
                        spio_data, gpio_data, uart_data;
        reg     [31:0]   io_data;
        reg     [31:0]   io_data;
        reg     [(BAW-1):0]      bus_err_addr;
        reg     [(BAW-1):0]      bus_err_addr;
 
 
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
        assign  wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
                                ||(uart_ack)
 
`ifdef  INCLUDE_RTC
`ifdef  INCLUDE_RTC
                                ||(rtc_ack)
                                ||(rtc_ack)
`endif
`endif
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
                                ||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
        assign  wb_stall = ((io_sel)&&(io_stall))
        assign  wb_stall = ((io_sel)&&(io_stall))
Line 174... Line 198...
                        : ((mem_ack)?mem_data
                        : ((mem_ack)?mem_data
                        : ((flash_ack)?flash_data
                        : ((flash_ack)?flash_data
                        : 32'h00))));
                        : 32'h00))));
        */
        */
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
                        : ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
 
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
                        : ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
                        : flash_data)); // if (flash_ack)
                        : ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
 
        // Addresses ...
        // Addresses ...
        //      0000 xxxx       configuration/control registers
        //      0000 xxxx       configuration/control registers
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
Line 231... Line 254...
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                ~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
                                rtc_interrupt, scop_interrupt,
                                rtc_interrupt, scop_interrupt,
                                wb_err, button_int };
                                wb_err, button_int };
 
 
        wire    [31:0]   pic_data;
        wire    [31:0]   pic_data;
        icontrol #(11)  pic(i_clk, 1'b0,
        icontrol #(11)  pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
                                (wb_cyc)&&(wb_stb)&&(io_sel)
 
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                                        &&(wb_addr[3:0]==4'h0)&&(wb_we),
                        wb_data, pic_data, int_vector, w_interrupt);
                        wb_data, pic_data, int_vector, w_interrupt);
 
 
        initial bus_err_addr = `DATESTAMP;
        initial bus_err_addr = `DATESTAMP;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (wb_err)
                if (wb_err)
                        bus_err_addr <= wb_addr;
                        bus_err_addr <= wb_addr;
 
 
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
        wire            zta_ack, zta_stall, ztb_ack, ztb_stall;
        wire    [31:0]   timer_a, timer_b;
        wire    [31:0]   timer_a, timer_b;
        ziptimer        zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
        ziptimer        #(32,20)
 
                zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                wb_we, wb_data, zta_ack, zta_stall, timer_a,
                                tmra_int);
                                tmra_int);
        ziptimer        zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
        ziptimer        #(32,20)
 
                zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
                                (wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
                                wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
                                tmrb_int);
                                tmrb_int);
 
 
        wire    [31:0]   rtc_data;
        wire    [31:0]   rtc_data;
Line 264... Line 288...
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
                r_rtc_ack <= ((wb_stb)&&(rtc_sel));
        assign  rtc_ack = r_rtc_ack;
        assign  rtc_ack = r_rtc_ack;
 
 
        rtclight
        rtclight
                #(32'h35afe5)           // 80 MHz clock
                #(32'h35afe5,23)        // 80 MHz clock
                thetime(i_clk, wb_cyc,
                thetime(i_clk, wb_cyc,
                        ((wb_stb)&&(rtc_sel)), wb_we,
                        ((wb_stb)&&(rtc_sel)), wb_we,
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
                        { 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
                        rtc_interrupt, ppd);
                        rtc_interrupt, ppd);
`else
`else
Line 331... Line 355...
        assign  o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
        assign  o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
 
 
        initial o_tx_stb = 1'b0;
        initial o_tx_stb = 1'b0;
        initial o_tx_data = 8'h00;
        initial o_tx_data = 8'h00;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
                if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
                begin
                begin
                        o_tx_data <= wb_data[7:0];
                        o_tx_data <= wb_data[7:0];
                        o_tx_stb <= 1'b1;
                        o_tx_stb <= 1'b1;
                end
                end
                else if ((o_tx_stb)&&(~i_tx_busy))
                else if ((o_tx_stb)&&(~i_tx_busy))
Line 344... Line 368...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rx_stb)
                if (i_rx_stb)
                        r_rx_data <= i_rx_data;
                        r_rx_data <= i_rx_data;
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                if((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
                if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
                        rx_rdy <= i_rx_stb;
                        rx_rdy <= i_rx_stb;
                else if (i_rx_stb)
                else if (i_rx_stb)
                        rx_rdy <= (rx_rdy | i_rx_stb);
                        rx_rdy <= (rx_rdy | i_rx_stb);
        end
        end
 
        assign  o_uart_rts = (~rx_rdy);
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
        assign  uart_data = { 23'h0, ~rx_rdy, r_rx_data };
        always @(posedge i_clk)
        //
                uart_ack<= ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
        // uart_ack gets returned as part of io_ack, since that happens when
 
        // io_sel and wb_stb are defined
 
        //
 
        // always @(posedge i_clk)
 
                // uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
 
 
 
 
 
 
        //
        //
        //      FLASH MEMORY CONFIGURATION ACCESS
        //      FLASH MEMORY CONFIGURATION ACCESS
        //
        //
        wire    flash_cs_n, flash_sck, flash_mosi;
        wire    flash_cs_n, flash_sck, flash_mosi;
        wbqspiflash #(24)       flashmem(i_clk,
        wbqspiflash #(24)       flashmem(i_clk,
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
                        wb_addr[21:0], wb_data,
                        wb_addr[(24-3):0], wb_data,
                flash_ack, flash_stall, flash_data,
                flash_ack, flash_stall, flash_data,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
                flash_interrupt);
                flash_interrupt);
 
 
        //
        //
Line 389... Line 418...
 
 
 
 
        //
        //
        //      ON-CHIP RAM MEMORY ACCESS
        //      ON-CHIP RAM MEMORY ACCESS
        //
        //
 
`ifdef  IMPLEMENT_ONCHIP_RAM
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
        memdev  #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
                        wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
 
`else
 
        assign  mem_data = 32'h00;
 
        assign  mem_stall = 1'b0;
 
        reg     r_mem_ack;
 
        always @(posedge i_clk)
 
                r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
 
        assign  mem_ack = r_mem_ack;
 
`endif
 
 
        //
        //
        //
        //
        //      WISHBONE SCOPE
        //      WISHBONE SCOPE
        //
        //
Line 404... Line 442...
        wire    [31:0]   scop_cfg_data;
        wire    [31:0]   scop_cfg_data;
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef  CFG_SCOPE
`ifdef  CFG_SCOPE
        wire            scop_cfg_trigger;
        wire            scop_cfg_trigger;
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
        wbscope #(5'h6) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
                // Wishbone interface
                // Wishbone interface
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
                i_clk, wb_cyc, (wb_stb)&&(scop_sel),
                                wb_we, wb_addr[0], wb_data,
                                wb_we, wb_addr[0], wb_data,
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
                scop_cfg_interrupt);
                scop_cfg_interrupt);
 
`else
 
        reg     r_scop_cfg_ack;
 
        always @(posedge i_clk)
 
                r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
 
        assign  scop_cfg_ack = r_scop_cfg_ack;
 
        assign  scop_cfg_data = 32'h000;
 
        assign  scop_cfg_stall= 1'b0;
`endif
`endif
 
 
        assign  scop_interrupt = scop_cfg_interrupt;
        assign  scop_interrupt = scop_cfg_interrupt;
        assign  scop_ack   = scop_cfg_ack;
        assign  scop_ack   = scop_cfg_ack;
        assign  scop_stall = scop_cfg_stall;
        assign  scop_stall = scop_cfg_stall;
        assign  scop_data  = scop_cfg_data;
        assign  scop_data  = scop_cfg_data;
 
 
endmodule
endmodule
 
 
// 0x8684 interrupts ...???
 
 
 
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