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Line 1... |
//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: busmaster.v
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// Filename: busmaster.v
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//
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//
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// Project: FPGA library development (S6 development board)
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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// Copyright: 2015
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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//
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`include "builddate.v"
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`include "builddate.v"
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//
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//
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`define NO_ZIP_WBU_DELAY
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`define INCLUDE_ZIPPY
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`define INCLUDE_ZIPPY
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`define IMPLEMENT_ONCHIP_RAM
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`define IMPLEMENT_ONCHIP_RAM // 2804 w/o after synthesis
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define FANCY_ICAP_ACCESS
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`define FANCY_ICAP_ACCESS
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`endif
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`endif
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`define FLASH_ACCESS
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`define FLASH_ACCESS
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`define CFG_SCOPE
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// `define CFG_SCOPE // About 204 LUTs, at 2^6 addresses
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`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
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`define INCLUDE_RTC // About 90 LUTs
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module busmaster(i_clk, i_rst,
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module busmaster(i_clk, i_rst,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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o_uart_rts,
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// The SPI Flash lines
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// The SPI Flash lines
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The board I/O
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// The board I/O
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i_btn, o_led, o_pwm, o_pwm_aux,
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i_btn, o_led, o_pwm, o_pwm_aux,
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// Keypad connections
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// Keypad connections
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| Line 43... |
Line 67... |
input i_rx_stb;
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input i_rx_stb;
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input [7:0] i_rx_data;
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input [7:0] i_rx_data;
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output reg o_tx_stb;
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output reg o_tx_stb;
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output reg [7:0] o_tx_data;
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output reg [7:0] o_tx_data;
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input i_tx_busy;
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input i_tx_busy;
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output wire o_uart_rts;
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// SPI flash control
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// SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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| Line 142... |
Line 167... |
wire rtc_ack, rtc_stall;
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wire rtc_ack, rtc_stall;
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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assign rtc_stall = 1'b0;
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assign rtc_stall = 1'b0;
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`endif
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`endif
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
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reg io_ack, uart_ack;
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reg io_ack;
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
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spio_data, gpio_data, uart_data;
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spio_data, gpio_data, uart_data;
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reg [31:0] io_data;
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reg [31:0] io_data;
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reg [(BAW-1):0] bus_err_addr;
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reg [(BAW-1):0] bus_err_addr;
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
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assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
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||(uart_ack)
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`ifdef INCLUDE_RTC
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`ifdef INCLUDE_RTC
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||(rtc_ack)
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||(rtc_ack)
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`endif
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`endif
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
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assign wb_stall = ((io_sel)&&(io_stall))
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assign wb_stall = ((io_sel)&&(io_stall))
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| Line 174... |
Line 198... |
: ((mem_ack)?mem_data
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: ((mem_ack)?mem_data
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: ((flash_ack)?flash_data
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: ((flash_ack)?flash_data
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: 32'h00))));
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: 32'h00))));
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*/
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*/
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assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
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: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
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: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
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: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
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: flash_data)); // if (flash_ack)
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: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
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assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
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assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
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// Addresses ...
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// Addresses ...
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// 0000 xxxx configuration/control registers
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// 0000 xxxx configuration/control registers
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
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| Line 231... |
Line 254... |
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
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rtc_interrupt, scop_interrupt,
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rtc_interrupt, scop_interrupt,
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wb_err, button_int };
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wb_err, button_int };
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wire [31:0] pic_data;
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wire [31:0] pic_data;
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icontrol #(11) pic(i_clk, 1'b0,
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icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
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(wb_cyc)&&(wb_stb)&&(io_sel)
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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&&(wb_addr[3:0]==4'h0)&&(wb_we),
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wb_data, pic_data, int_vector, w_interrupt);
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wb_data, pic_data, int_vector, w_interrupt);
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initial bus_err_addr = `DATESTAMP;
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initial bus_err_addr = `DATESTAMP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_err)
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if (wb_err)
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bus_err_addr <= wb_addr;
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bus_err_addr <= wb_addr;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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wire zta_ack, zta_stall, ztb_ack, ztb_stall;
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wire [31:0] timer_a, timer_b;
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wire [31:0] timer_a, timer_b;
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ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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ziptimer #(32,20)
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zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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wb_we, wb_data, zta_ack, zta_stall, timer_a,
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tmra_int);
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tmra_int);
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ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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ziptimer #(32,20)
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zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
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wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
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tmrb_int);
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tmrb_int);
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wire [31:0] rtc_data;
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wire [31:0] rtc_data;
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Line 288... |
always @(posedge i_clk)
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always @(posedge i_clk)
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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r_rtc_ack <= ((wb_stb)&&(rtc_sel));
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assign rtc_ack = r_rtc_ack;
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assign rtc_ack = r_rtc_ack;
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rtclight
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rtclight
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#(32'h35afe5) // 80 MHz clock
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#(32'h35afe5,23) // 80 MHz clock
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thetime(i_clk, wb_cyc,
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thetime(i_clk, wb_cyc,
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((wb_stb)&&(rtc_sel)), wb_we,
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((wb_stb)&&(rtc_sel)), wb_we,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
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rtc_interrupt, ppd);
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rtc_interrupt, ppd);
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`else
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`else
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Line 355... |
assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
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assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
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initial o_tx_stb = 1'b0;
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initial o_tx_stb = 1'b0;
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initial o_tx_data = 8'h00;
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initial o_tx_data = 8'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
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if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
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begin
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begin
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o_tx_data <= wb_data[7:0];
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o_tx_data <= wb_data[7:0];
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o_tx_stb <= 1'b1;
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o_tx_stb <= 1'b1;
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end
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end
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else if ((o_tx_stb)&&(~i_tx_busy))
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else if ((o_tx_stb)&&(~i_tx_busy))
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| Line 344... |
Line 368... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rx_stb)
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if (i_rx_stb)
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r_rx_data <= i_rx_data;
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r_rx_data <= i_rx_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
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if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
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rx_rdy <= i_rx_stb;
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rx_rdy <= i_rx_stb;
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else if (i_rx_stb)
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else if (i_rx_stb)
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rx_rdy <= (rx_rdy | i_rx_stb);
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rx_rdy <= (rx_rdy | i_rx_stb);
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end
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end
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assign o_uart_rts = (~rx_rdy);
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assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
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assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
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always @(posedge i_clk)
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//
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uart_ack<= ((wb_cyc)&&(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
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// uart_ack gets returned as part of io_ack, since that happens when
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// io_sel and wb_stb are defined
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//
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// always @(posedge i_clk)
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// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
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//
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//
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// FLASH MEMORY CONFIGURATION ACCESS
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// FLASH MEMORY CONFIGURATION ACCESS
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//
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//
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wire flash_cs_n, flash_sck, flash_mosi;
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wire flash_cs_n, flash_sck, flash_mosi;
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wbqspiflash #(24) flashmem(i_clk,
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wbqspiflash #(24) flashmem(i_clk,
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wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
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wb_addr[21:0], wb_data,
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wb_addr[(24-3):0], wb_data,
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flash_ack, flash_stall, flash_data,
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flash_ack, flash_stall, flash_data,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
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flash_interrupt);
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flash_interrupt);
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//
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//
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| Line 389... |
Line 418... |
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//
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//
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// ON-CHIP RAM MEMORY ACCESS
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// ON-CHIP RAM MEMORY ACCESS
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//
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//
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`ifdef IMPLEMENT_ONCHIP_RAM
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memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
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memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
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wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
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wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
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`else
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assign mem_data = 32'h00;
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assign mem_stall = 1'b0;
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reg r_mem_ack;
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always @(posedge i_clk)
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r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
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assign mem_ack = r_mem_ack;
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`endif
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//
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//
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//
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//
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// WISHBONE SCOPE
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// WISHBONE SCOPE
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//
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//
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| Line 404... |
Line 442... |
wire [31:0] scop_cfg_data;
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wire [31:0] scop_cfg_data;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
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`ifdef CFG_SCOPE
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`ifdef CFG_SCOPE
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wire scop_cfg_trigger;
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wire scop_cfg_trigger;
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
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wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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wbscope #(5'h6) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cfg_interrupt);
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scop_cfg_interrupt);
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`else
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reg r_scop_cfg_ack;
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always @(posedge i_clk)
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r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
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assign scop_cfg_ack = r_scop_cfg_ack;
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assign scop_cfg_data = 32'h000;
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assign scop_cfg_stall= 1'b0;
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`endif
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`endif
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assign scop_interrupt = scop_cfg_interrupt;
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assign scop_interrupt = scop_cfg_interrupt;
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assign scop_ack = scop_cfg_ack;
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assign scop_ack = scop_cfg_ack;
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assign scop_stall = scop_cfg_stall;
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assign scop_stall = scop_cfg_stall;
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assign scop_data = scop_cfg_data;
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assign scop_data = scop_cfg_data;
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endmodule
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endmodule
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// 0x8684 interrupts ...???
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No newline at end of file
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No newline at end of file
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