| Line 2... |
Line 2... |
//
|
//
|
// Filename: busmaster.v
|
// Filename: busmaster.v
|
//
|
//
|
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
|
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
|
//
|
//
|
// Purpose:
|
// Purpose: This is the highest level, simulatable, file in the S6SoC
|
|
// project--of that portion of the project that includes the
|
|
// ZipCPU. This portion therefore contains references to all of the
|
|
// masters (ZipCPU) and slaves (flash, block RAM, I/O, Scope) on the
|
|
// wishbone bus, and connects them all together. Hence, this contains
|
|
// the wishbone interconnect logic as well.
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
| Line 33... |
Line 38... |
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
//
|
|
`include "builddate.v"
|
`include "builddate.v"
|
//
|
//
|
`define INCLUDE_ZIPPY
|
|
`define IMPLEMENT_ONCHIP_RAM
|
`define IMPLEMENT_ONCHIP_RAM
|
`ifndef VERILATOR
|
|
`define FANCY_ICAP_ACCESS
|
|
`endif
|
|
`define FLASH_ACCESS
|
`define FLASH_ACCESS
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
|
// `define COMPRESSED_SCOPE
|
// `define COMPRESSED_SCOPE
|
`define INCLUDE_SECOND_TIMER
|
|
`define SECOND_TIMER_IS_WATCHDOG
|
|
// `define INCLUDE_RTC // About 90 LUTs
|
|
// `define FULL_BUSERR_CALCULATION
|
|
`define INCLUDE_CPU_RESET_LOGIC
|
`define INCLUDE_CPU_RESET_LOGIC
|
module busmaster(i_clk, i_rst,
|
module busmaster(i_clk, i_rst,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_uart, o_uart_rts_n, o_uart, i_uart_cts_n,
|
o_uart_cts,
|
|
// The SPI Flash lines
|
// The SPI Flash lines
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
// The board I/O
|
// The board I/O
|
i_btn, o_led, o_pwm, o_pwm_aux,
|
i_btn, o_led, o_pwm, o_pwm_aux,
|
// Keypad connections
|
// Keypad connections
|
i_kp_row, o_kp_col,
|
i_kp_row, o_kp_col,
|
// UART control
|
|
o_uart_setup,
|
|
// GPIO lines
|
// GPIO lines
|
i_gpio, o_gpio);
|
i_gpio, o_gpio);
|
parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
|
parameter BUS_ADDRESS_WIDTH=23,
|
CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
|
ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
|
ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
|
CMOD_ZIPCPU_RESET_ADDRESS=32'h1200000,
|
|
UART_SETUP = 31'd25;
|
|
localparam ZA=ZIP_ADDRESS_WIDTH,
|
|
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
|
|
// 2^14 bytes requires a LGMEMSZ of 14, and 12 address bits ranging from
|
|
// 0 to 11. As with many other devices, the wb_cyc line is more for
|
|
// form than anything else--it is ignored by the memory itself.
|
|
localparam LGMEMSZ=14; // Takes 8 BLKRAM16 elements for LGMEMSZ=14
|
|
// As with the memory size, the flash size is also measured in log_2 of
|
|
// the number of bytes.
|
|
localparam LGFLASHSZ = 24;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
input i_rx_stb;
|
// UART parameters
|
input [7:0] i_rx_data;
|
input i_uart, i_uart_cts_n;
|
output reg o_tx_stb;
|
output wire o_uart, o_uart_rts_n;
|
output reg [7:0] o_tx_data;
|
|
input i_tx_busy;
|
|
output wire o_uart_cts;
|
|
// SPI flash control
|
// SPI flash control
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire [3:0] o_qspi_dat;
|
output wire [3:0] o_qspi_dat;
|
input [3:0] i_qspi_dat;
|
input [3:0] i_qspi_dat;
|
output wire [1:0] o_qspi_mod;
|
output wire [1:0] o_qspi_mod;
|
| Line 85... |
Line 85... |
output wire o_pwm;
|
output wire o_pwm;
|
output wire [1:0] o_pwm_aux;
|
output wire [1:0] o_pwm_aux;
|
// Keypad
|
// Keypad
|
input [3:0] i_kp_row;
|
input [3:0] i_kp_row;
|
output wire [3:0] o_kp_col;
|
output wire [3:0] o_kp_col;
|
// UART control
|
|
output wire [29:0] o_uart_setup;
|
|
// GPIO liines
|
// GPIO liines
|
input [15:0] i_gpio;
|
input [15:0] i_gpio;
|
output wire [15:0] o_gpio;
|
output wire [15:0] o_gpio;
|
|
|
|
|
| Line 99... |
Line 97... |
// Master wishbone wires
|
// Master wishbone wires
|
//
|
//
|
//
|
//
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
|
wire [31:0] wb_data, wb_idata;
|
wire [31:0] wb_data, wb_idata;
|
|
wire [3:0] wb_sel;
|
wire [(BAW-1):0] wb_addr;
|
wire [(BAW-1):0] wb_addr;
|
wire [5:0] io_addr;
|
|
assign io_addr = {
|
|
wb_addr[22], // Flash
|
|
wb_addr[13], // RAM
|
|
wb_addr[11], // RTC
|
|
wb_addr[10], // CFG
|
|
wb_addr[ 9], // SCOPE
|
|
wb_addr[ 8] }; // I/O
|
|
|
|
// Wires going to devices
|
// Wires going to devices
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
| Line 132... |
Line 123... |
wire zip_ack, zip_stall, zip_err;
|
wire zip_ack, zip_stall, zip_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire [(BAW-1):0] dwb_addr;
|
wire [(BAW-1):0] dwb_addr;
|
wire [31:0] dwb_odata;
|
wire [31:0] dwb_odata;
|
|
|
// wire [31:0] zip_debug;
|
wire cpu_reset, watchdog_int;
|
//
|
//
|
// We'll define our RESET_ADDRESS to be halfway through our flash memory.
|
|
// `define CMOD_ZIPCPU_RESET_ADDRESS 23'h600000
|
|
//
|
|
// Ahm, No. We can actually do much better than that. Our toplevel *.bit file
|
|
// only takes up only 335kB. Let's give it some room to grow to 1024 kB. Then
|
|
// 23 can start our ROM at 23'h400100
|
|
//
|
|
// Not so fast. In hindsight, we really want to be able to adjust the load and
|
|
// the program separately. So, instead, let's place our RESET address at the
|
|
// second flash erase block. That way, we can change our program code found
|
|
// in the flash without needing to change our FPGA load and vice versa.
|
|
//
|
|
// 23'h404000
|
|
wire cpu_reset, tmrb_int;
|
|
`ifdef INCLUDE_CPU_RESET_LOGIC
|
`ifdef INCLUDE_CPU_RESET_LOGIC
|
reg btn_reset, x_button, r_button;
|
reg btn_reset, x_button, r_button;
|
initial btn_reset = 1'b0;
|
initial btn_reset = 1'b0;
|
initial x_button = 1'b0;
|
initial x_button = 1'b0;
|
initial r_button = 1'b0;
|
initial r_button = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
x_button <= i_btn[1];
|
x_button <= i_btn[1];
|
r_button <= x_button;
|
r_button <= x_button;
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
btn_reset <= ((r_button)&&(zip_cpu_int))||(watchdog_int);
|
btn_reset <= ((r_button)&&(zip_cpu_int))||(tmrb_int);
|
|
`else
|
|
btn_reset <= ((r_button)&&(zip_cpu_int));
|
|
`endif
|
|
end
|
end
|
assign cpu_reset = btn_reset;
|
assign cpu_reset = btn_reset;
|
`else
|
`else
|
assign cpu_reset = 1'b0;
|
assign cpu_reset = 1'b0;
|
`endif
|
`endif
|
|
|
zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
|
zipbones #(CMOD_ZIPCPU_RESET_ADDRESS,ZA,6)
|
thecpu(i_clk, btn_reset, // 1'b0,
|
swic(i_clk, btn_reset, // 1'b0,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data,
|
wb_cyc, wb_stb, wb_we, w_zip_addr, wb_data, wb_sel,
|
wb_ack, wb_stall, wb_idata, wb_err,
|
wb_ack, wb_stall, wb_idata, wb_err,
|
w_interrupt, zip_cpu_int,
|
w_interrupt, zip_cpu_int,
|
// Debug wishbone interface -- not really used
|
// Debug wishbone interface -- not really used
|
1'b0, 1'b0,1'b0, 1'b0, 32'h00,
|
1'b0, 1'b0,1'b0, 1'b0, 32'h00,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
|
| Line 185... |
Line 158... |
assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
|
assign wb_addr = { {(BAW-ZA){1'b0}}, w_zip_addr };
|
else
|
else
|
assign wb_addr = w_zip_addr;
|
assign wb_addr = w_zip_addr;
|
endgenerate
|
endgenerate
|
|
|
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
|
|
rtc_sel, none_sel, many_sel;
|
// Signals to build/detect bus errors
|
|
wire none_sel, many_sel;
|
|
|
|
wire io_sel, flash_sel, flctl_sel, scop_sel, mem_sel;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
|
wire flash_ack, scop_ack, cfg_ack, mem_ack, many_ack;
|
wire rtc_ack, rtc_stall;
|
|
`ifdef INCLUDE_RTC
|
|
assign rtc_stall = 1'b0;
|
|
`endif
|
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
|
reg io_ack;
|
reg io_ack;
|
|
|
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
|
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
|
spio_data, gpio_data, uart_data;
|
spio_data, gpio_data, uart_data;
|
reg [31:0] io_data;
|
reg [31:0] io_data;
|
reg [(BAW-1):0] bus_err_addr;
|
reg [(BAW-1):0] bus_err_addr;
|
|
//
|
|
// wb_ack
|
|
//
|
|
// The returning wishbone ack is equal to the OR of every component that
|
|
// might possibly produce an acknowledgement, gated by the CYC line. To
|
|
// add new components, OR their acknowledgements in here.
|
|
//
|
|
// Note the reference to none_sel. If nothing is selected, the result
|
|
// is an error. Here, we do nothing more than insure that the erroneous
|
|
// request produces an ACK ... if it was ever made, rather than stalling
|
|
// the bus.
|
|
//
|
|
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
|
|
`ifdef INCLUDE_RTC
|
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)
|
||(rtc_ack)
|
|
`endif
|
|
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
|
||(mem_ack)||(flash_ack)||((none_sel)&&(1'b1)));
|
|
|
|
//
|
|
// wb_stall
|
|
//
|
|
// The returning wishbone stall line really depends upon what device
|
|
// is requested. Thus, if a particular device is selected, we return
|
|
// the stall line for that device.
|
|
//
|
|
// To add a new device, simply and that devices select and stall lines
|
|
// together, and OR the result with the massive OR logic below.
|
|
//
|
assign wb_stall = ((io_sel)&&(io_stall))
|
assign wb_stall = ((io_sel)&&(io_stall))
|
||((scop_sel)&&(scop_stall))
|
||((scop_sel)&&(scop_stall))
|
||((cfg_sel)&&(cfg_stall))
|
|
||((mem_sel)&&(mem_stall))
|
||((mem_sel)&&(mem_stall))
|
`ifdef INCLUDE_RTC
|
|
||((rtc_sel)&&(rtc_stall))
|
|
`endif
|
|
||((flash_sel||flctl_sel)&&(flash_stall));
|
||((flash_sel||flctl_sel)&&(flash_stall));
|
// (none_sel)&&(1'b0)
|
// (none_sel)&&(1'b0)
|
|
|
/*
|
//
|
assign wb_idata = (io_ack)?io_data
|
// wb_idata
|
: ((scop_ack)?scop_data
|
//
|
: ((cfg_ack)?cfg_data
|
// This is the data returned on the bus. Here, we select between a
|
: ((mem_ack)?mem_data
|
// series of bus sources to select what data to return. The basic
|
: ((flash_ack)?flash_data
|
// logic is simply this: the data we return is the data for which the
|
: 32'h00))));
|
// ACK line is high.
|
*/
|
//
|
|
// The last item on the list is chosen by default if no other ACK's are
|
|
// true. Although we might choose to return zeros in that case, by
|
|
// returning something we can skimp a touch on the logic.
|
|
//
|
|
// To add another device, add another ack check, and another closing
|
|
// parenthesis.
|
|
//
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
|
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
|
: ((mem_ack)?(mem_data)
|
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
|
: flash_data);
|
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
|
|
|
//
|
|
// wb_err
|
|
//
|
|
// This is the bus error signal. It should never be true, but practice
|
|
// teaches us otherwise. Here, we allow for three basic errors:
|
|
//
|
|
// 1. STB is true, but no devices are selected
|
|
//
|
|
// This is the null pointer reference bug. If you try to access
|
|
// something on the bus, at an address with no mapping, the bus
|
|
// should produce an error--such as if you try to access something
|
|
// at zero.
|
|
//
|
|
// 2. STB is true, and more than one device is selected
|
|
//
|
|
// (This can be turned off, if you design this file well. For
|
|
// this line to be true means you have a design flaw.)
|
|
//
|
|
// 3. If more than one ACK is every true at any given time.
|
|
//
|
|
// This is a bug of bus usage, combined with a subtle flaw in the
|
|
// WB pipeline definition. You can issue bus requests, one per
|
|
// clock, and if you cross device boundaries with your requests,
|
|
// you may have things come back out of order (not detected here)
|
|
// or colliding on return (detected here). The solution to this
|
|
// problem is to make certain that any burst request does not cross
|
|
// device boundaries. This is a requirement of whoever (or
|
|
// whatever) drives the bus.
|
|
//
|
|
assign wb_err = ((wb_stb)&&(none_sel || many_sel)) || many_ack;
|
|
|
// Addresses ...
|
// Addresses ...
|
// 0000 xxxx configuration/control registers
|
//
|
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
|
// dev_sel
|
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
|
//
|
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
|
// The device select lines
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
|
//
|
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
|
//
|
// zip_sel is not on the bus at this point
|
|
`ifdef INCLUDE_RTC
|
|
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
|
|
`endif
|
|
assign mem_sel =((wb_cyc)&&(io_addr[5:4]==2'h1));
|
|
assign flash_sel=((wb_cyc)&&(io_addr[5]));
|
|
|
|
`ifdef FULL_BUSERR_CALCULATION
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&
|
//
|
((io_addr==6'h0)
|
// The skipaddr bitfield below is our cheaters way of handling
|
||((~io_addr[5])&&(|wb_addr[22:14]))
|
// device selection. We grab particular wires from the bus to do
|
||((io_addr[5:4]==2'b00)&&(|wb_addr[12])))
|
// this, and ignore all others. While this may lead to some
|
);
|
// surprising results for the CPU when it tries to access an
|
assign many_sel =((wb_cyc)&&(wb_stb)&&(
|
// inappropriate address, it also minimizes our logic while also
|
{3'h0, io_sel}
|
// placing every address at the right address. The only problem is
|
+{3'h0, flctl_sel}
|
// ... devices will also be at some unexpected addresses, but ... this
|
+{3'h0, scop_sel}
|
// is still within our spec.
|
+{3'h0, cfg_sel}
|
//
|
+{3'h0, rtc_sel}
|
wire [3:0] skipaddr;
|
+{3'h0, mem_sel}
|
assign skipaddr = {
|
+{3'h0, flash_sel} > 1));
|
wb_addr[(LGFLASHSZ-2)], // Flash
|
|
wb_addr[(LGMEMSZ-2)], // RAM
|
assign many_ack =((wb_cyc)&&(
|
wb_addr[ 9], // SCOPE
|
{3'h0, io_ack}
|
wb_addr[ 8] }; // I/O
|
+{3'h0, scop_ack}
|
//
|
+{3'h0, cfg_ack}
|
// This might not be the most efficient way in hardware, but it will
|
`ifdef INCLUDE_RTC
|
// work for our purposes here. There are two phantom bits for each
|
+{3'h0, rtc_ack}
|
// of these ... bits that tell the CPU which byte within the word, and
|
`endif
|
// another phantom bit because we allocated a minimum of two words to
|
+{3'h0, mem_ack}
|
// every device.
|
+{3'h0, flash_ack} > 1));
|
//
|
|
wire idle_n;
|
|
`ifdef ZERO_ON_IDLE
|
|
assign idle_n = wb_stb;
|
`else
|
`else
|
assign many_ack = 1'b0;
|
assign idle_n = 1'b1;
|
assign many_sel = 1'b0;
|
|
assign none_sel =((wb_cyc)&&(wb_stb)&&(
|
|
(io_addr[5:4]==2'h0)
|
|
&&(~io_addr[0])
|
|
`ifdef INCLUDE_RTC
|
|
&&(~io_addr[3])
|
|
`endif
|
`endif
|
`ifdef FANCY_ICAP_ACCESS
|
|
&&(~io_addr[2])
|
// `define ZERO_ON_IDLE
|
`endif
|
`ifdef ZERO_ON_IDLE
|
`ifdef DBG_SCOPE
|
assign idle_n = (wb_cyc)&&(wb_stb);
|
&&(~io_addr[1])
|
`else
|
`endif
|
assign idle_n = 1'b1;
|
));
|
|
`endif
|
`endif
|
wire flash_interrupt, scop_interrupt, tmra_int,
|
assign io_sel =((idle_n)&&(skipaddr[3:0]==4'h1));
|
rtc_interrupt, gpio_int, pwm_int, keypad_int,button_int;
|
assign scop_sel =((idle_n)&&(skipaddr[3:1]==3'h1)); // = 4'h2
|
|
assign flctl_sel= 1'b0; // ((wb_cyc)&&(skipaddr[3:0]==4'h3));
|
|
assign mem_sel =((idle_n)&&(skipaddr[3:2]==2'h1));
|
|
assign flash_sel=((idle_n)&&(skipaddr[3]));
|
|
|
|
//
|
|
// none_sel
|
|
//
|
|
// This wire is true if wb_stb is true and no device is selected. This
|
|
// is an error condition, but here we present the logic to test for it.
|
|
//
|
|
//
|
|
// If you add another device, add another OR into the select lines
|
|
// associated with this term.
|
|
//
|
|
assign none_sel =((wb_stb)&&(skipaddr==4'h0));
|
|
|
//
|
//
|
|
// many_sel
|
|
//
|
|
// This should *never* be true .... unless you mess up your address
|
|
// decoding logic. Since I've done that before, I test/check for it
|
|
// here.
|
//
|
//
|
|
// To add a new device here, simply add it to the list. Make certain
|
|
// that the width of the add, however, is greater than the number
|
|
// of devices below. Hence, for 3 devices, you will need an add
|
|
// at least 3 bits in width, for 7 devices you will need at least 4
|
|
// bits, etc.
|
|
//
|
|
// Because this add uses the {} operator, the individual components to
|
|
// it are by default unsigned ... just as we would like.
|
|
//
|
|
// There's probably another easier/better/faster/cheaper way to do this,
|
|
// but I haven't found any such that are also easier to adjust with
|
|
// new devices. I'm open to options.
|
|
//
|
|
assign many_sel = 1'b0;
|
|
|
|
//
|
|
// many_ack
|
|
//
|
|
// Normally this would capture the error when multiple things creates acks
|
|
// at the same time. The S6 is small, though, and doesn't have the logic
|
|
// we need to do this right. Hence we just declare (and hope) that this
|
|
// will never be true and work with that.
|
|
//
|
|
assign many_ack = 1'b0;
|
|
|
|
|
|
wire flash_interrupt, scop_interrupt, timer_int,
|
|
gpio_int, pwm_int, keypad_int,button_int;
|
|
|
|
|
|
//
|
|
// bus_err_addr
|
|
//
|
|
// We'd like to know, after the fact, what (if any) address caused a
|
|
// bus error. So ... if we get a bus error, let's record the address
|
|
// on the bus for later analysis.
|
|
//
|
|
initial bus_err_addr = 0;
|
|
always @(posedge i_clk)
|
|
if (wb_err)
|
|
bus_err_addr <= wb_addr;
|
|
//
|
|
// Interrupt processing
|
|
//
|
|
// The interrupt controller will be used to tell us if any interrupts
|
|
// take place.
|
|
//
|
|
// To add more interrupts, you can just add more wires to this
|
|
// int_vector.
|
//
|
//
|
reg rx_rdy;
|
reg rx_rdy;
|
wire [10:0] int_vector;
|
wire [10:0] int_vector;
|
assign int_vector = {
|
assign int_vector = {
|
gpio_int, pwm_int, keypad_int,
|
gpio_int, pwm_int, keypad_int,
|
(~o_tx_stb), rx_rdy,
|
(!tx_stb), rx_rdy,
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
1'b0, timer_int,
|
1'b0,
|
1'b0, scop_interrupt,
|
`else
|
|
tmrb_int,
|
|
`endif
|
|
tmra_int,
|
|
rtc_interrupt, scop_interrupt,
|
|
wb_err, button_int };
|
wb_err, button_int };
|
|
|
wire [31:0] pic_data;
|
wire [31:0] pic_data;
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
&&(wb_addr[3:0]==4'h0)&&(wb_we),
|
wb_data, pic_data, int_vector, w_interrupt);
|
wb_data, pic_data, int_vector, w_interrupt);
|
|
|
initial bus_err_addr = 0; // `DATESTAMP;
|
wire [31:0] timer_data, watchdog_data;
|
always @(posedge i_clk)
|
|
if (wb_err)
|
|
bus_err_addr <= wb_addr;
|
|
|
|
wire [31:0] timer_a, timer_b;
|
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
|
ziptimer #(32,31,1)
|
ziptimer #(32,31,1)
|
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
|
thetimer(i_clk, 1'b0, 1'b1, wb_cyc,
|
`ifdef INCLUDE_SECOND_TIMER
|
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
|
`else
|
wb_we, wb_data, zta_ack, zta_stall, timer_data,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:1]==3'h1),
|
timer_int);
|
`endif
|
|
wb_we, wb_data, zta_ack, zta_stall, timer_a,
|
|
tmra_int);
|
|
`ifdef INCLUDE_SECOND_TIMER
|
|
`ifdef SECOND_TIMER_IS_WATCHDOG
|
|
ziptimer #(32,31,0)
|
ziptimer #(32,31,0)
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
watchdog(i_clk, cpu_reset, 1'b1, wb_cyc,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
|
tmrb_int);
|
|
`else
|
|
ziptimer #(32,31,1)
|
|
zipt_b(i_clk, cpu_reset, 1'b1, wb_cyc,
|
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
|
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
|
wb_we, wb_data, ztb_ack, ztb_stall, watchdog_data,
|
tmrb_int);
|
watchdog_int);
|
`endif
|
|
`else
|
|
// assign timer_b = 32'h000;
|
|
assign timer_b = timer_a;
|
|
assign tmrb_int = 1'b0;
|
|
`endif
|
|
|
|
wire [31:0] rtc_data;
|
|
`ifdef INCLUDE_RTC
|
|
wire rtcd_ack, rtcd_stall, ppd;
|
|
// rtcdate thedate(i_clk, ppd, wb_cyc, (wb_stb)&&(io_sel), wb_we,
|
|
// wb_data, rtcd_ack, rtcd_stall, date_data);
|
|
reg r_rtc_ack;
|
|
initial r_rtc_ack = 1'b0;
|
|
always @(posedge i_clk)
|
|
r_rtc_ack <= ((wb_stb)&&(rtc_sel));
|
|
assign rtc_ack = r_rtc_ack;
|
|
|
|
rtclight
|
|
#(23'h35afe5,23,0,0) // 80 MHz clock
|
|
thetime(i_clk, wb_cyc,
|
|
((wb_stb)&&(rtc_sel)), wb_we,
|
|
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
|
|
rtc_interrupt, ppd);
|
|
`else
|
|
assign rtc_interrupt = 1'b0;
|
|
assign rtc_data = 32'h00;
|
|
assign rtc_ack = 1'b0;
|
|
`endif
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(wb_addr[3:0])
|
case(wb_addr[3:0])
|
4'h0: io_data <= pic_data;
|
4'h0: io_data <= pic_data;
|
4'h1: io_data <= { {(32-BAW){1'b0}}, bus_err_addr };
|
4'h1: io_data <= { {(30-BAW){1'b0}}, bus_err_addr, 2'b00 };
|
4'h2: io_data <= timer_a;
|
4'h2: io_data <= timer_data;
|
4'h3: io_data <= timer_b;
|
4'h3: io_data <= watchdog_data;
|
4'h4: io_data <= pwm_data;
|
4'h4: io_data <= pwm_data;
|
4'h5: io_data <= spio_data;
|
4'h5: io_data <= spio_data;
|
4'h6: io_data <= gpio_data;
|
4'h6: io_data <= gpio_data;
|
4'h7: io_data <= uart_data;
|
4'h7: io_data <= uart_data;
|
default: io_data <= `DATESTAMP;
|
default: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
// 4'h8: io_data <= `DATESTAMP;
|
endcase
|
endcase
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
io_ack <= (wb_cyc)&&(wb_stb)&&(io_sel);
|
io_ack <= (wb_stb)&&(io_sel);
|
assign io_stall = 1'b0;
|
assign io_stall = 1'b0;
|
|
|
wire pwm_ack, pwm_stall;
|
wire pwm_ack, pwm_stall;
|
wbpwmaudio #(14'd10000,2,0,14)
|
wbpwmaudio #(14'd10000,2,0,14)
|
theaudio(i_clk, wb_cyc,
|
theaudio(i_clk, wb_cyc,
|
| Line 398... |
Line 431... |
|
|
//
|
//
|
// Special Purpose I/O: Keypad, button, LED status and control
|
// Special Purpose I/O: Keypad, button, LED status and control
|
//
|
//
|
wire [3:0] w_led;
|
wire [3:0] w_led;
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),wb_we,
|
spio thespio(i_clk, wb_cyc,(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h5),
|
wb_data, spio_data, o_kp_col, i_kp_row, i_btn, w_led,
|
wb_we, wb_data, spio_data,
|
|
o_kp_col, i_kp_row, i_btn, w_led,
|
keypad_int, button_int);
|
keypad_int, button_int);
|
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
|
assign o_led = { w_led[3]|w_interrupt,w_led[2]|zip_cpu_int,w_led[1:0] };
|
|
|
//
|
//
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
// General purpose (sort of) I/O: (Bottom two bits robbed in each
|
| Line 413... |
Line 447... |
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h6), wb_we,
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
wb_data, gpio_data, i_gpio, o_gpio, gpio_int);
|
|
|
//
|
//
|
//
|
//
|
|
// UART device: our console
|
|
//
|
|
//
|
|
wire [30:0] uart_setup;
|
|
//
|
|
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, rx_stb;
|
|
wire [7:0] rx_data;
|
|
//
|
|
assign uart_setup = UART_SETUP;
|
|
//
|
|
rxuart #(UART_SETUP)
|
|
rcvuart(i_clk, 1'b0, uart_setup, i_uart, rx_stb, rx_data,
|
|
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
|
|
//
|
|
wire tx_break, tx_busy;
|
|
reg tx_stb;
|
|
reg [7:0] tx_data;
|
|
assign tx_break = 1'b0;
|
|
txuart #(UART_SETUP)
|
|
tcvuart(i_clk, 1'b0, uart_setup, tx_break, tx_stb, tx_data,
|
|
i_uart_cts_n, o_uart, tx_busy);
|
|
|
|
//
|
// Rudimentary serial port control
|
// Rudimentary serial port control
|
//
|
//
|
reg [7:0] r_rx_data;
|
reg [7:0] r_rx_data;
|
// Baud rate is set by clock rate / baud rate.
|
// Baud rate is set by clock rate / baud rate.
|
// Thus, 80MHz / 115200MBau
|
|
// = 694.4, or about 0x2b6.
|
|
// although the CPU might struggle to keep up at this speed without a
|
|
// hardware buffer.
|
|
//
|
|
// We'll add the flag for two stop bits.
|
|
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
|
|
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
|
|
|
|
initial o_tx_stb = 1'b0;
|
initial tx_stb = 1'b0;
|
initial o_tx_data = 8'h00;
|
initial tx_data = 8'h00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
|
begin
|
begin
|
o_tx_data <= wb_data[7:0];
|
tx_data <= wb_data[7:0];
|
o_tx_stb <= 1'b1;
|
tx_stb <= 1'b1;
|
end
|
end
|
else if ((o_tx_stb)&&(~i_tx_busy))
|
else if ((tx_stb)&&(!tx_busy))
|
o_tx_stb <= 1'b0;
|
tx_stb <= 1'b0;
|
initial rx_rdy = 1'b0;
|
initial rx_rdy = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rx_stb)
|
if (rx_stb)
|
r_rx_data <= i_rx_data;
|
r_rx_data <= rx_data;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
|
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(!wb_we))
|
rx_rdy <= i_rx_stb;
|
rx_rdy <= rx_stb;
|
else if (i_rx_stb)
|
else if (rx_stb)
|
rx_rdy <= (rx_rdy | i_rx_stb);
|
rx_rdy <= (rx_rdy | rx_stb);
|
end
|
end
|
assign o_uart_cts = (~rx_rdy);
|
assign o_uart_rts_n = (rx_rdy);
|
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
|
assign uart_data = { 23'h0, !rx_rdy, r_rx_data };
|
//
|
//
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// uart_ack gets returned as part of io_ack, since that happens when
|
// io_sel and wb_stb are defined
|
// io_sel and wb_stb are defined
|
//
|
//
|
// always @(posedge i_clk)
|
// always @(posedge i_clk)
|
| Line 461... |
Line 510... |
|
|
|
|
//
|
//
|
// FLASH MEMORY CONFIGURATION ACCESS
|
// FLASH MEMORY CONFIGURATION ACCESS
|
//
|
//
|
wbqspiflash #(24) flashmem(i_clk,
|
`ifdef FLASH_ACCESS
|
|
wbqspiflash #(LGFLASHSZ) flashmem(i_clk,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
wb_addr[(24-3):0], wb_data,
|
wb_addr[(LGFLASHSZ-3):0], wb_data,
|
flash_ack, flash_stall, flash_data,
|
flash_ack, flash_stall, flash_data,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
flash_interrupt);
|
flash_interrupt);
|
|
|
//
|
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
|
//
|
|
wire [31:0] cfg_scope;
|
|
`ifdef FANCY_ICAP_ACCESS
|
|
wbicape6 fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
|
wb_addr[5:0], wb_data,
|
|
cfg_ack, cfg_stall, cfg_data,
|
|
cfg_scope);
|
|
`else
|
`else
|
reg r_cfg_ack;
|
reg r_flash_ack;
|
|
initial r_flash_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_cfg_ack <= (wb_cyc)&&(cfg_sel)&&(wb_stb);
|
r_flash_ack <= (wb_stb)&&((flash_sel)||(flctl_sel));
|
assign cfg_ack = r_cfg_ack;
|
|
assign cfg_stall = 1'b0;
|
|
assign cfg_data = 32'h00;
|
|
assign cfg_scope = 32'h00;
|
|
`endif
|
|
|
|
|
assign flash_ack = r_flash_ack;
|
|
assign flash_stall = 1'b0;
|
|
assign flash_data = 32'h0000;
|
|
assign flash_interrupt = 1'b0;
|
|
|
|
assign o_qspi_sck = 1'b1;
|
|
assign o_qspi_cs_n = 1'b1;
|
|
assign o_qspi_mod = 2'b01;
|
|
assign o_qspi_dat = 4'b1111;
|
|
`endif
|
|
|
//
|
//
|
// ON-CHIP RAM MEMORY ACCESS
|
// ON-CHIP RAM MEMORY ACCESS
|
//
|
//
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
`ifdef IMPLEMENT_ONCHIP_RAM
|
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
memdev #(.LGMEMSZ(LGMEMSZ))
|
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
|
ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
|
|
wb_addr[(LGMEMSZ-3):0], wb_data, wb_sel,
|
|
mem_ack, mem_stall, mem_data);
|
`else
|
`else
|
assign mem_data = 32'h00;
|
assign mem_data = 32'h00;
|
assign mem_stall = 1'b0;
|
assign mem_stall = 1'b0;
|
reg r_mem_ack;
|
reg r_mem_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
|
r_mem_ack <= (wb_stb)&&(mem_sel);
|
assign mem_ack = r_mem_ack;
|
assign mem_ack = r_mem_ack;
|
`endif
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// WISHBONE SCOPE
|
// WISHBONE SCOPE
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
wire [31:0] scop_cfg_data;
|
wire [31:0] scop_cpu_data;
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
`ifdef DBG_SCOPE
|
`ifdef DBG_SCOPE
|
wire scop_cfg_trigger;
|
|
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
|
|
// wire scop_trigger = scop_cfg_trigger;
|
|
wire scop_trigger = (zip_cpu_int) || (cpu_reset);
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wire scop_trigger = (zip_cpu_int) || (cpu_reset);
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`ifdef COMPRESSED_SCOPE
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`ifdef COMPRESSED_SCOPE
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wbscopc #(5'ha)
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wbscopc #(5'ha)
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`else
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`else
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wbscope #(5'ha)
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wbscope #(.LGMEM(5'h6), .HOLDOFFBITS(9))
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`endif
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`endif
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wbcfgscope(i_clk, 1'b1, scop_trigger,
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cpuscope(i_clk, 1'b1, scop_trigger,
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`ifdef COMPRESSED_SCOPE
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`ifdef COMPRESSED_SCOPE
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// cfg_scope[30:0],
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// cfg_scope[30:0],
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zip_scope_data[30:0],
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zip_scope_data[30:0],
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`else
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`else
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// cfg_scope[31:0],
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// cfg_scope[31:0],
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zip_scope_data[31:0],
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zip_scope_data[31:0],
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`endif
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`endif
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// Wishbone interface
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// Wishbone interface
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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i_clk, wb_cyc, (wb_stb)&&(scop_sel),
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wb_we, wb_addr[0], wb_data,
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wb_we, wb_addr[0], wb_data,
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scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
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scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
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scop_cfg_interrupt);
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scop_cpu_interrupt);
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`else
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`else
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reg r_scop_cfg_ack;
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reg r_scop_cpu_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
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r_scop_cpu_ack <= (wb_stb)&&(scop_sel);
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assign scop_cfg_ack = r_scop_cfg_ack;
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assign scop_cpu_ack = r_scop_cpu_ack;
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assign scop_cfg_data = 32'h000;
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assign scop_cpu_data = 32'h000;
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assign scop_cfg_stall= 1'b0;
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assign scop_cpu_stall= 1'b0;
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`endif
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`endif
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|
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assign scop_interrupt = scop_cfg_interrupt;
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assign scop_interrupt = scop_cpu_interrupt;
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assign scop_ack = scop_cfg_ack;
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assign scop_ack = scop_cpu_ack;
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assign scop_stall = scop_cfg_stall;
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assign scop_stall = scop_cpu_stall;
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assign scop_data = scop_cfg_data;
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assign scop_data = scop_cpu_data;
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|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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