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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: cpudefs.v
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// Filename: cpudefs.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`ifndef CPUDEFS_H
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`ifndef CPUDEFS_H
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`define CPUDEFS_H
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`define CPUDEFS_H
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//
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//
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//
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//
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// The first couple options control the Zip CPU instruction set, and how
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// The first couple options control the Zip CPU instruction set, and how
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// unit. As I'm not there yet, it just catches illegal instructions and
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// unit. As I'm not there yet, it just catches illegal instructions and
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// interrupts the CPU on any such instruction--when defined. Otherwise,
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// interrupts the CPU on any such instruction--when defined. Otherwise,
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// illegal instructions are quietly ignored and their behaviour is ...
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// illegal instructions are quietly ignored and their behaviour is ...
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// undefined. (Many get treated like NOOPs ...)
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// undefined. (Many get treated like NOOPs ...)
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//
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//
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// I recommend setting this flag, although it can be taken out if area is
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// I recommend setting this flag so highly, that I'm likely going to remove
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// critical ...
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// the option to turn this off in future versions of this CPU.
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//
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//
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`define OPT_ILLEGAL_INSTRUCTION
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`define OPT_ILLEGAL_INSTRUCTION
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//
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//
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//
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//
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//
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//
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// includes the multiply. (This parameter may still be overridden, as with
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// includes the multiply. (This parameter may still be overridden, as with
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// any parameter ...) If the multiply is not included and
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// any parameter ...) If the multiply is not included and
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// instruction that will then trip the illegal instruction trap.
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// instruction that will then trip the illegal instruction trap.
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//
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//
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// Either not defining this value, or defining it to zero will disable the
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// hardware multiply. A value of '1' will cause the multiply to occurr in one
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// clock cycle only--often at the expense of the rest of the CPUs speed.
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// A value of 2 will cause the multiply to have a single delay cycle, 3 will
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// have two delay cycles, and 4 (or more) will have 3 delay cycles.
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//
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//
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`define OPT_MULTIPLY 2
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//
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`define OPT_MULTIPLY 4
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//
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//
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//
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//
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//
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//
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// OPT_DIVIDE controls whether or not the divide instruction is built and
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// OPT_DIVIDE controls whether or not the divide instruction is built and
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// included into the ZipCPU by default. Set this option and a parameter will
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// included into the ZipCPU by default. Set this option and a parameter will
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//
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//
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// `define OPT_IMPLEMENT_FPU
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// `define OPT_IMPLEMENT_FPU
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//
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//
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//
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//
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//
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//
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// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set
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// is in use. The new instruction set contains space for floating point
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// operations, signed and unsigned divide instructions, as well as bit reversal
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// and ... at least two other operations yet to be defined. The decoder alone
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// uses about 70 fewer LUTs, although in practice this works out to 12 fewer
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// when all works out in the wash. Further, floating point and divide
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// instructions will cause an illegal instruction exception if they are not
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// implemented--so software capability can be built to use these instructions
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// immediately, even if the hardware is not yet ready.
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//
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// This option is likely to go away in the future, obsoleting the previous
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// instruction set, so I recommend setting this option and switching to the
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// new instruction set as soon as possible.
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//
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//
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`define OPT_NEW_INSTRUCTION_SET
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// The instruction set defines an optional compressed instruction set (CIS)
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// complement. These were at one time erroneously called Very Long Instruction
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// Words. They are more appropriately referred to as compressed instructions.
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// The compressed instruction format allows two instructions to be packed into
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// the same instruction word. Some instructions can be compressed, not all.
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// Compressed instructions take the same time to complete. Set OPT_CIS to
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// include these double instructions as part of the instruction set. These
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// instructions are designed to get more code density from the instruction set,
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// and to hopefully take some pain off of the performance of the pre-fetch and
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// instruction cache.
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//
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// These new instructions, however, also necessitate a change in the Zip
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// CPU--the Zip CPU can no longer execute instructions atomically. It must
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// now execute non-CIS instructions, or CIS instruction pairs, atomically.
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// This logic has been added into the ZipCPU, but it has not (yet) been
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// tested thoroughly.
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//
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//
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// Oh, and the debugger and the simulator also need to be updated as well
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// to properly handle these.
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//
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//
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// `define OPT_CIS // Adds about 80 LUTs on a Spartan 6
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//
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//
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//
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//
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//
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//
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//
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//
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and
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//
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//
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`define OPT_PIPELINED_BUS_ACCESS
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`define OPT_PIPELINED_BUS_ACCESS
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//
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//
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//
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//
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//
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//
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`ifdef OPT_NEW_INSTRUCTION_SET
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//
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//
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//
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// The new instruction set also defines a set of very long instruction words.
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// Well, calling them "very long" instruction words is probably a misnomer,
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// although we're going to do it. They're really 2x16-bit instructions---
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// instruction words that pack two instructions into one word. (2x14 bit
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// really--'cause you need a bit to note the instruction is a 2x instruction,
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// and then 3-bits for the condition codes ...) Set OPT_VLIW to include these
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// double instructions as part of the new instruction set. These allow a single
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// instruction to contain two instructions within. These instructions are
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// designed to get more code density from the instruction set, and to hopefully
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// take some pain off of the performance of the pre-fetch and instruction cache.
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//
|
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// These new instructions, however, also necessitate a change in the Zip
|
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// CPU--the Zip CPU can no longer execute instructions atomically. It must
|
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// now execute non-VLIW instructions, or VLIW instruction pairs, atomically.
|
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// This logic has been added into the ZipCPU, but it has not (yet) been
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// tested thoroughly.
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//
|
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// Oh, and the assembler, the debugger, and the object file dumper, and the
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// simulator all need to be updated as well ....
|
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//
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`define OPT_VLIW
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//
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//
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//
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//
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`endif // OPT_NEW_INSTRUCTION_SET
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//
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//
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//
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//
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`endif // OPT_SINGLE_FETCH
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`endif // OPT_SINGLE_FETCH
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//
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//
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//
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//
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