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https://opencores.org/ocsvn/s6soc/s6soc/trunk
[/] [s6soc/] [trunk/] [rtl/] [cpu/] [cpuops.v] - Diff between revs 46 and 51
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| Rev 46 |
Rev 51 |
| Line 126... |
Line 126... |
end
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end
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assign mpy_result = r_mpy_a_input * r_mpy_b_input;
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assign mpy_result = r_mpy_a_input * r_mpy_b_input;
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assign mpybusy = 1'b0;
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assign mpybusy = 1'b0;
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initial mpypipe = 1'b0;
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reg mpypipe;
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reg mpypipe;
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initial mpypipe = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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mpypipe <= 1'b0;
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mpypipe <= 1'b0;
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else
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else
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mpypipe <= (this_is_a_multiply_op);
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mpypipe <= (this_is_a_multiply_op);
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| Line 203... |
Line 203... |
reg [31:0] r_mpy_a_input, r_mpy_b_input;
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
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reg r_mpy_signed;
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reg r_mpy_signed;
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reg [2:0] mpypipe;
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reg [2:0] mpypipe;
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// First clock, latch in the inputs
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// First clock, latch in the inputs
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initial mpypipe = 3'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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// mpypipe indicates we have a multiply in the
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// mpypipe indicates we have a multiply in the
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// pipeline. In this case, the multiply
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// pipeline. In this case, the multiply
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// pipeline is a two stage pipeline, so we need
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// pipeline is a two stage pipeline, so we need
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