URL
https://opencores.org/ocsvn/s6soc/s6soc/trunk
[/] [s6soc/] [trunk/] [rtl/] [cpu/] [zipcpu.v] - Diff between revs 7 and 11
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 7 |
Rev 11 |
| Line 867... |
Line 867... |
|
|
initial r_op_lock = 1'b0;
|
initial r_op_lock = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_op_lock <= 1'b0;
|
r_op_lock <= 1'b0;
|
else if ((op_ce)&&(dcd_lock))
|
else if (op_ce)
|
r_op_lock <= 1'b1;
|
r_op_lock <= (dcd_lock)&&(~clear_pipeline);
|
else if ((op_ce)||(clear_pipeline))
|
|
r_op_lock <= 1'b0;
|
|
assign op_lock = r_op_lock;
|
assign op_lock = r_op_lock;
|
|
|
end else begin
|
end else begin
|
assign op_lock_stall = 1'b0;
|
assign op_lock_stall = 1'b0;
|
assign op_lock = 1'b0;
|
assign op_lock = 1'b0;
|
| Line 1178... |
Line 1176... |
wire bus_lock;
|
wire bus_lock;
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
reg r_bus_lock;
|
reg [1:0] r_bus_lock;
|
initial r_bus_lock = 1'b0;
|
initial r_bus_lock = 2'b00;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_bus_lock <= 1'b0;
|
r_bus_lock <= 2'b00;
|
else if ((op_ce)&&(op_lock))
|
else if ((op_ce)&&(op_lock))
|
r_bus_lock <= 1'b1;
|
r_bus_lock <= 2'b11;
|
else if (~opvalid_mem)
|
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
|
r_bus_lock <= 1'b0;
|
r_bus_lock <= r_bus_lock + 2'b11;
|
assign bus_lock = r_bus_lock;
|
assign bus_lock = |r_bus_lock;
|
end else begin
|
end else begin
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
end endgenerate
|
end endgenerate
|
`else
|
`else
|
assign bus_lock = 1'b0;
|
assign bus_lock = 1'b0;
|
| Line 1638... |
Line 1636... |
else if ((dcd_early_branch)&&(~clear_pipeline))
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
pf_pc <= dcd_branch_pc + 1;
|
pf_pc <= dcd_branch_pc + 1;
|
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
|
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
`else
|
`else
|
else if ((alu_pc_valid)&&(~clear_pipeline))
|
else if (((alu_pc_valid)&&(~clear_pipeline))||(mem_pc_valid))
|
pf_pc <= alu_pc;
|
pf_pc <= alu_pc;
|
`endif
|
`endif
|
|
|
initial new_pc = 1'b1;
|
initial new_pc = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.