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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [ziptimer.v] - Diff between revs 2 and 4

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        initial o_wb_ack = 1'b0;
        initial o_wb_ack = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
        assign  o_wb_stall = 1'b0;
        assign  o_wb_stall = 1'b0;
 
 
 
        generate
 
        if (VW < BW-1)
        assign  o_wb_data = { r_auto_reload, r_value };
        assign  o_wb_data = { r_auto_reload, r_value };
 
        else
 
                assign  o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
 
        endgenerate
 
 
endmodule
endmodule
 
 
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