| Line 82... |
Line 82... |
reg r_running;
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reg r_running;
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wire wb_write;
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wire wb_write;
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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wire auto_reload;
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wire auto_reload, need_reload;
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wire [(VW-1):0] reload_value;
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wire [(VW-1):0] reload_value;
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initial r_running = 1'b0;
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initial r_running = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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| Line 97... |
Line 97... |
r_running <= 1'b0;
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r_running <= 1'b0;
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generate
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generate
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if (RELOADABLE != 0)
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if (RELOADABLE != 0)
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begin
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begin
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reg r_auto_reload;
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reg r_auto_reload, r_need_reload;
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reg [(VW-1):0] r_reload_value;
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reg [(VW-1):0] r_reload_value;
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initial r_auto_reload = 1'b0;
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initial r_auto_reload = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (wb_write)
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if (wb_write)
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r_auto_reload <= (i_wb_data[(BW-1)]);
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r_auto_reload <= (i_wb_data[(BW-1)]);
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assign auto_reload = r_auto_reload;
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assign auto_reload = r_auto_reload;
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| Line 114... |
Line 113... |
// than zero, set the auto-reload value
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// than zero, set the auto-reload value
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
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r_reload_value <= i_wb_data[(VW-1):0];
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r_reload_value <= i_wb_data[(VW-1):0];
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assign reload_value = r_reload_value;
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assign reload_value = r_reload_value;
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initial r_need_reload = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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r_need_reload <= 1'b0;
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else if ((i_ce)&&(auto_reload))
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r_need_reload <= (i_ce)
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&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
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assign need_reload = r_need_reload;
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end else begin
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end else begin
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assign auto_reload = 1'b0;
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assign auto_reload = 1'b0;
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assign reload_value = 0;
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assign reload_value = 0;
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assign need_reload = 1'b0;
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end endgenerate
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end endgenerate
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reg [(VW-1):0] r_value;
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reg [(VW-1):0] r_value;
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initial r_value = 0;
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initial r_value = 0;
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