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[/] [s6soc/] [trunk/] [rtl/] [cpu/] [ziptimer.v] - Diff between revs 24 and 42

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Rev 24 Rev 42
Line 82... Line 82...
        reg                     r_running;
        reg                     r_running;
 
 
        wire    wb_write;
        wire    wb_write;
        assign  wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
        assign  wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
 
        wire    auto_reload;
        wire                    auto_reload, need_reload;
        wire    [(VW-1):0]       reload_value;
        wire    [(VW-1):0]       reload_value;
 
 
        initial r_running = 1'b0;
        initial r_running = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
Line 97... Line 97...
                        r_running <= 1'b0;
                        r_running <= 1'b0;
 
 
        generate
        generate
        if (RELOADABLE != 0)
        if (RELOADABLE != 0)
        begin
        begin
                reg     r_auto_reload;
                reg                     r_auto_reload, r_need_reload;
                reg     [(VW-1):0]       r_reload_value;
                reg     [(VW-1):0]       r_reload_value;
 
 
                initial r_auto_reload = 1'b0;
                initial r_auto_reload = 1'b0;
 
 
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (wb_write)
                        if (wb_write)
                                r_auto_reload <= (i_wb_data[(BW-1)]);
                                r_auto_reload <= (i_wb_data[(BW-1)]);
 
 
                assign  auto_reload = r_auto_reload;
                assign  auto_reload = r_auto_reload;
Line 114... Line 113...
                // than zero, set the auto-reload value
                // than zero, set the auto-reload value
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
                        if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
                                r_reload_value <= i_wb_data[(VW-1):0];
                                r_reload_value <= i_wb_data[(VW-1):0];
                assign  reload_value = r_reload_value;
                assign  reload_value = r_reload_value;
 
 
 
                initial r_need_reload = 1'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                r_need_reload <= 1'b0;
 
                        else if ((i_ce)&&(auto_reload))
 
                                r_need_reload <= (i_ce)
 
                                        &&(r_value == { {(VW-1){1'b0}}, 1'b1 });
 
 
 
                assign need_reload = r_need_reload;
        end else begin
        end else begin
                assign  auto_reload = 1'b0;
                assign  auto_reload = 1'b0;
                assign  reload_value = 0;
                assign  reload_value = 0;
 
                assign  need_reload = 1'b0;
        end endgenerate
        end endgenerate
 
 
 
 
        reg     [(VW-1):0]       r_value;
        reg     [(VW-1):0]       r_value;
        initial r_value = 0;
        initial r_value = 0;

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