/////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// Filename: rxuart.v
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// Filename: rxuart.v
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//
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//
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// Project: FPGA library development (Spartan 3E development board)
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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//
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// Purpose: Receive and decode inputs from a single UART line.
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// Purpose: Receive and decode inputs from a single UART line.
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//
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//
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//
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//
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// To interface with this module, connect it to your system clock,
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// To interface with this module, connect it to your system clock,
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// pass it the 32 bit setup register (defined below) and the UART
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// pass it the 32 bit setup register (defined below) and the UART
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// input. When data becomes available, the o_wr line will be asserted
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// input. When data becomes available, the o_wr line will be asserted
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// for one clock cycle. On parity or frame errors, the o_parity_err
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// for one clock cycle. On parity or frame errors, the o_parity_err
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// or o_frame_err lines will be asserted. Likewise, on a break
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// or o_frame_err lines will be asserted. Likewise, on a break
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// condition, o_break will be asserted. These lines are self clearing.
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// condition, o_break will be asserted. These lines are self clearing.
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//
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//
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// There is a synchronous reset line, logic high.
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// There is a synchronous reset line, logic high.
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//
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//
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// Now for the setup register. The register is 32 bits, so that this
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// Now for the setup register. The register is 32 bits, so that this
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// UART may be set up over a 32-bit bus.
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// UART may be set up over a 32-bit bus.
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//
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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// for a six bit word, or 2'b11 for a five bit word.
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//
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// Set this to one to expect two stop bits, zero for one.
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// Set this to one to expect two stop bits, zero for one.
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//
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//
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// i_setup[26] Indicates whether or not a parity bit exists. Set this
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// i_setup[26] Indicates whether or not a parity bit exists. Set this
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// to 1'b1 to include parity.
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// to 1'b1 to include parity.
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//
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//
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// i_setup[25] Indicates whether or not the parity bit is fixed. Set
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// i_setup[25] Indicates whether or not the parity bit is fixed. Set
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// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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// parity to be set based upon data. (Both assume the parity
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// parity to be set based upon data. (Both assume the parity
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// enable value is set.)
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// enable value is set.)
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//
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//
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// i_setup[24] This bit is ignored if parity is not used. Otherwise,
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// i_setup[24] This bit is ignored if parity is not used. Otherwise,
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// in the case of a fixed parity bit, this bit indicates whether
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// in the case of a fixed parity bit, this bit indicates whether
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// mark (1'b1) or space (1'b0) parity is used. Likewise if the
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// mark (1'b1) or space (1'b0) parity is used. Likewise if the
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// parity is not fixed, a 1'b1 selects even parity, and 1'b0
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// parity is not fixed, a 1'b1 selects even parity, and 1'b0
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// selects odd.
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// selects odd.
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//
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//
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// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
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// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
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// So, for example, if you have a 200 MHz clock and wish to
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// So, for example, if you have a 200 MHz clock and wish to
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// run your UART at 9600 baud, you would take 200 MHz and divide
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// run your UART at 9600 baud, you would take 200 MHz and divide
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// by 9600 to set this value to 24'd20834. Likewise if you wished
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// by 9600 to set this value to 24'd20834. Likewise if you wished
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// to run this serial port at 115200 baud from a 200 MHz clock,
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// to run this serial port at 115200 baud from a 200 MHz clock,
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// you would set the value to 24'd1736
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// you would set the value to 24'd1736
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//
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//
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// Thus, to set the UART for the common setting of an 8-bit word,
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// Thus, to set the UART for the common setting of an 8-bit word,
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// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
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// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
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// would want to set the setup value to:
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// would want to set the setup value to:
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//
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//
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// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
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// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
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// 32'h005161 // For 9600 baud, 8 bit, no parity
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// 32'h005161 // For 9600 baud, 8 bit, no parity
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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// Copyright: 2015
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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/////////////////////////////////////////////////////////////////////////
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//
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//
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// This software is the ownership of Gisselquist Technology, LLC, and as
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////////////////////////////////////////////////////////////////////////////////
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// such it is proprietary. It is provided without any warrantees, either
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// express or implied, so that it may be tested. Upon completion, I ask
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// that working code be returned and not further distributed beyond those
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// that it is originally offered to.
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//
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//
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// Thank you.
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//
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//
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// States: (@ baud counter == 0)
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// States: (@ baud counter == 0)
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// 0 First bit arrives
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// 0 First bit arrives
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// ..7 Bits arrive
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// ..7 Bits arrive
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// 8 Stop bit (x1)
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// 8 Stop bit (x1)
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// 9 Stop bit (x2)
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// 9 Stop bit (x2)
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/// c break condition
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/// c break condition
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// d Waiting for the channel to go high
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// d Waiting for the channel to go high
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// e Waiting for the reset to complete
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// e Waiting for the reset to complete
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// f Idle state
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// f Idle state
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ONE 4'h1
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`define RXU_BIT_ONE 4'h1
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`define RXU_BIT_TWO 4'h2
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`define RXU_BIT_TWO 4'h2
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`define RXU_BIT_THREE 4'h3
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`define RXU_BIT_THREE 4'h3
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`define RXU_BIT_FOUR 4'h4
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`define RXU_BIT_FOUR 4'h4
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`define RXU_BIT_FIVE 4'h5
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`define RXU_BIT_FIVE 4'h5
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`define RXU_BIT_SIX 4'h6
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`define RXU_BIT_SIX 4'h6
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`define RXU_BIT_SEVEN 4'h7
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`define RXU_BIT_SEVEN 4'h7
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`define RXU_PARITY 4'h8
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`define RXU_PARITY 4'h8
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`define RXU_STOP 4'h9
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`define RXU_STOP 4'h9
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`define RXU_SECOND_STOP 4'ha
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`define RXU_SECOND_STOP 4'ha
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// Unused 4'hb
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// Unused 4'hb
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// Unused 4'hc
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// Unused 4'hc
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`define RXU_BREAK 4'hd
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`define RXU_BREAK 4'hd
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`define RXU_RESET_IDLE 4'he
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`define RXU_RESET_IDLE 4'he
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`define RXU_IDLE 4'hf
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`define RXU_IDLE 4'hf
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module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
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module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
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o_parity_err, o_frame_err, o_ck_uart);
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o_parity_err, o_frame_err, o_ck_uart);
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// parameter // CLOCKS_PER_BAUD = 25'd004340,
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// parameter // CLOCKS_PER_BAUD = 25'd004340,
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// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
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// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
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// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
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// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
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// 8 data bits, no parity, (at least 1) stop bit
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// 8 data bits, no parity, (at least 1) stop bit
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [29:0] i_setup;
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input [29:0] i_setup;
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input i_uart;
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input i_uart;
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output reg o_wr;
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output reg o_wr;
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output reg [7:0] o_data;
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output reg [7:0] o_data;
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output reg o_break;
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output reg o_break;
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output reg o_parity_err, o_frame_err;
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output reg o_parity_err, o_frame_err;
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output wire o_ck_uart;
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output wire o_ck_uart;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign data_bits = r_setup[29:28];
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assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
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assign dblstop = r_setup[27];
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assign use_parity = r_setup[26];
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assign use_parity = r_setup[26];
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assign fixd_parity = r_setup[25];
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assign fixd_parity = r_setup[25];
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assign parity_even = r_setup[24];
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assign parity_even = r_setup[24];
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign half_baud = { 5'h00, r_setup[23:1] };
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assign half_baud = { 5'h00, r_setup[23:1] };
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reg q_uart, qq_uart, ck_uart;
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reg q_uart, qq_uart, ck_uart;
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initial q_uart = 1'b0;
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initial q_uart = 1'b0;
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initial qq_uart = 1'b0;
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initial qq_uart = 1'b0;
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initial ck_uart = 1'b0;
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initial ck_uart = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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q_uart <= i_uart;
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q_uart <= i_uart;
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qq_uart <= q_uart;
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qq_uart <= q_uart;
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ck_uart <= qq_uart;
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ck_uart <= qq_uart;
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end
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end
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assign o_ck_uart = ck_uart;
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assign o_ck_uart = ck_uart;
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reg [27:0] chg_counter;
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reg [27:0] chg_counter;
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initial chg_counter = 28'h00;
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initial chg_counter = 28'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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chg_counter <= 28'h00;
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chg_counter <= 28'h00;
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else if (qq_uart != ck_uart)
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else if (qq_uart != ck_uart)
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chg_counter <= 28'h00;
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chg_counter <= 28'h00;
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else if (chg_counter < break_condition)
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else if (chg_counter < break_condition)
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chg_counter <= chg_counter + 1;
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chg_counter <= chg_counter + 1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
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o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
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reg [3:0] state;
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reg [3:0] state;
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reg [27:0] baud_counter;
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reg [27:0] baud_counter;
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reg [7:0] data_reg;
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reg [7:0] data_reg;
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reg calc_parity;
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reg calc_parity;
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initial o_wr = 1'b0;
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initial o_wr = 1'b0;
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initial state = `RXU_RESET_IDLE;
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initial state = `RXU_RESET_IDLE;
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initial o_parity_err = 1'b0;
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initial o_parity_err = 1'b0;
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initial o_frame_err = 1'b0;
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initial o_frame_err = 1'b0;
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// initial baud_counter = clocks_per_baud;
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// initial baud_counter = clocks_per_baud;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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begin
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begin
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o_wr <= 1'b0;
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o_wr <= 1'b0;
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o_data <= 8'h00;
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o_data <= 8'h00;
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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baud_counter <= clocks_per_baud; // Set, not reset
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baud_counter <= clocks_per_baud; // Set, not reset
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data_reg <= 8'h00;
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data_reg <= 8'h00;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (state == `RXU_RESET_IDLE)
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end else if (state == `RXU_RESET_IDLE)
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begin
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begin
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r_setup <= i_setup;
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r_setup <= i_setup;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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if ((ck_uart)&&(chg_counter >= break_condition))
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if ((ck_uart)&&(chg_counter >= break_condition))
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// Goto idle state from a reset
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// Goto idle state from a reset
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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else // Otherwise, stay in this condition 'til reset
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else // Otherwise, stay in this condition 'til reset
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if ((~ck_uart)&&(chg_counter >= break_condition))
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end else if ((~ck_uart)&&(chg_counter >= break_condition))
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begin // We are in a break condition
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begin // We are in a break condition
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state <= `RXU_BREAK;
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state <= `RXU_BREAK;
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o_wr <= 1'b0;
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o_wr <= 1'b0;
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o_data <= 8'h00;
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o_data <= 8'h00;
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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data_reg <= 8'h00;
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data_reg <= 8'h00;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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end else if (state == `RXU_BREAK)
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end else if (state == `RXU_BREAK)
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begin // Goto idle state following return ck_uart going high
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begin // Goto idle state following return ck_uart going high
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud - 28'h01;
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baud_counter <= clocks_per_baud - 28'h01;
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if (ck_uart)
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if (ck_uart)
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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else
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else
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state <= `RXU_BREAK;
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state <= `RXU_BREAK;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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r_setup <= i_setup;
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r_setup <= i_setup;
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end else if (state == `RXU_IDLE)
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end else if (state == `RXU_IDLE)
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begin // Idle state, independent of baud counter
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begin // Idle state, independent of baud counter
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud - 28'h01;
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baud_counter <= clocks_per_baud - 28'h01;
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if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
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if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
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begin
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begin
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// We are in the center of a valid start bit
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// We are in the center of a valid start bit
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case (data_bits)
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case (data_bits)
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2'b00: state <= `RXU_BIT_ZERO;
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2'b00: state <= `RXU_BIT_ZERO;
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2'b01: state <= `RXU_BIT_ONE;
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2'b01: state <= `RXU_BIT_ONE;
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2'b10: state <= `RXU_BIT_TWO;
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2'b10: state <= `RXU_BIT_TWO;
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2'b11: state <= `RXU_BIT_THREE;
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2'b11: state <= `RXU_BIT_THREE;
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endcase
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endcase
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end else // Otherwise, just stay here in idle
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end else // Otherwise, just stay here in idle
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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calc_parity <= 1'b0;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (baud_counter == 0)
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end else if (baud_counter == 0)
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begin
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begin
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baud_counter <= clocks_per_baud-28'h1;
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baud_counter <= clocks_per_baud-28'h1;
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if (state < `RXU_BIT_SEVEN)
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if (state < `RXU_BIT_SEVEN)
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begin
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begin
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// Data arrives least significant bit first.
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// Data arrives least significant bit first.
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// By the time this is clocked in, it's what
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// By the time this is clocked in, it's what
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// you'll have.
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// you'll have.
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data_reg <= { ck_uart, data_reg[7:1] };
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data_reg <= { ck_uart, data_reg[7:1] };
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calc_parity <= calc_parity ^ ck_uart;
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calc_parity <= calc_parity ^ ck_uart;
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o_data <= 8'h00;
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o_data <= 8'h00;
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o_wr <= 1'b0;
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o_wr <= 1'b0;
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state <= state + 1;
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state <= state + 1;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (state == `RXU_BIT_SEVEN)
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end else if (state == `RXU_BIT_SEVEN)
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begin
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begin
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data_reg <= { ck_uart, data_reg[7:1] };
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data_reg <= { ck_uart, data_reg[7:1] };
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calc_parity <= calc_parity ^ ck_uart;
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calc_parity <= calc_parity ^ ck_uart;
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o_data <= 8'h00;
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o_data <= 8'h00;
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o_wr <= 1'b0;
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o_wr <= 1'b0;
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state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
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state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
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o_parity_err <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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o_frame_err <= 1'b0;
|
end else if (state == `RXU_PARITY)
|
end else if (state == `RXU_PARITY)
|
begin
|
begin
|
if (fixd_parity)
|
if (fixd_parity)
|
o_parity_err <= (ck_uart ^ parity_even);
|
o_parity_err <= (ck_uart ^ parity_even);
|
else
|
else
|
o_parity_err <= ((parity_even && (calc_parity != ck_uart))
|
o_parity_err <= ((parity_even && (calc_parity != ck_uart))
|
||((~parity_even)&&(calc_parity==ck_uart)));
|
||((~parity_even)&&(calc_parity==ck_uart)));
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state <= `RXU_STOP;
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state <= `RXU_STOP;
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o_frame_err <= 1'b0;
|
o_frame_err <= 1'b0;
|
end else if (state == `RXU_STOP)
|
end else if (state == `RXU_STOP)
|
begin // Stop (or parity) bit(s)
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begin // Stop (or parity) bit(s)
|
case (data_bits)
|
case (data_bits)
|
2'b00: o_data <= data_reg;
|
2'b00: o_data <= data_reg;
|
2'b01: o_data <= { 1'b0, data_reg[7:1] };
|
2'b01: o_data <= { 1'b0, data_reg[7:1] };
|
2'b10: o_data <= { 2'b0, data_reg[7:2] };
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2'b10: o_data <= { 2'b0, data_reg[7:2] };
|
2'b11: o_data <= { 3'b0, data_reg[7:3] };
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2'b11: o_data <= { 3'b0, data_reg[7:3] };
|
endcase
|
endcase
|
o_wr <= 1'b1; // Pulse the write
|
o_wr <= 1'b1; // Pulse the write
|
o_frame_err <= (~ck_uart);
|
o_frame_err <= (~ck_uart);
|
if (~ck_uart)
|
if (~ck_uart)
|
state <= `RXU_RESET_IDLE;
|
state <= `RXU_RESET_IDLE;
|
else if (dblstop)
|
else if (dblstop)
|
state <= `RXU_SECOND_STOP;
|
state <= `RXU_SECOND_STOP;
|
else
|
else
|
state <= `RXU_IDLE;
|
state <= `RXU_IDLE;
|
// o_parity_err <= 1'b0;
|
// o_parity_err <= 1'b0;
|
end else // state must equal RX_SECOND_STOP
|
end else // state must equal RX_SECOND_STOP
|
begin
|
begin
|
if (~ck_uart)
|
if (~ck_uart)
|
begin
|
begin
|
o_frame_err <= 1'b1;
|
o_frame_err <= 1'b1;
|
state <= `RXU_RESET_IDLE;
|
state <= `RXU_RESET_IDLE;
|
end else begin
|
end else begin
|
state <= `RXU_IDLE;
|
state <= `RXU_IDLE;
|
o_frame_err <= 1'b0;
|
o_frame_err <= 1'b0;
|
end
|
end
|
o_parity_err <= 1'b0;
|
o_parity_err <= 1'b0;
|
end
|
end
|
end else begin
|
end else begin
|
o_wr <= 1'b0; // data_reg = data_reg
|
o_wr <= 1'b0; // data_reg = data_reg
|
baud_counter <= baud_counter - 28'd1;
|
baud_counter <= baud_counter - 28'd1;
|
o_parity_err <= 1'b0;
|
o_parity_err <= 1'b0;
|
o_frame_err <= 1'b0;
|
o_frame_err <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
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