`timescale 10ns / 100ps
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`timescale 10ns / 100ps
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: toplevel.v
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//
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// Project: CMod S6 System on a Chip, ZipCPU demonstration project
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//
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// Purpose: This is (supposed to be) the one Xilinx specific file in the
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// project. The idea is that all of the board specific logic,
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// the logic used in simulation, is kept in the busmaster.v file. It's
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// not quite true, since rxuart and txuart modules are instantiated here,
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// but it's mostly true.
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//
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// One thing that makes this module unique is that all of its inputs and
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// outputs must match those on the chip, as specified within the cmod.ucf
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// file (up one directory).
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//
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// Within this file you will find specific I/O for output pins, such as
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// the necessary adjustments to make an I2C port from GPIO pins, as well
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// as the clock management approach.
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module toplevel(i_clk_8mhz,
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module toplevel(i_clk_8mhz,
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o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
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o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
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i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
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i_uart, o_uart,
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i_uart, o_uart, i_uart_cts, o_uart_rts,
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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i_gpio, o_gpio,
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i_gpio, o_gpio,
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io_scl, io_sda);
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io_scl, io_sda);
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input i_clk_8mhz;
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input i_clk_8mhz;
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//
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//
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// Quad SPI Flash
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// Quad SPI Flash
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output wire o_qspi_cs_n;
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output wire o_qspi_cs_n;
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output wire o_qspi_sck;
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output wire o_qspi_sck;
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inout wire [3:0] io_qspi_dat;
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inout wire [3:0] io_qspi_dat;
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//
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//
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// General purpose I/O
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// General purpose I/O
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input [1:0] i_btn;
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input [1:0] i_btn;
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output wire [3:0] o_led;
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output wire [3:0] o_led;
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output wire o_pwm, o_pwm_shutdown_n, o_pwm_gain;
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output wire o_pwm, o_pwm_shutdown_n, o_pwm_gain;
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//
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//
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// and our serial port
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// and our serial port
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input i_uart;
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input i_uart;
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output wire o_uart;
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output wire o_uart;
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// and it's associated control wires
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input i_uart_cts;
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output wire o_uart_rts;
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// Our keypad
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// Our keypad
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input [3:0] i_kp_row;
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input [3:0] i_kp_row;
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output wire [3:0] o_kp_col;
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output wire [3:0] o_kp_col;
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// and our GPIO
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// and our GPIO
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input [15:2] i_gpio;
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input [15:2] i_gpio;
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output wire [15:2] o_gpio;
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output wire [15:2] o_gpio;
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// and our I2C port
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// and our I2C port
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inout io_scl, io_sda;
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inout io_scl, io_sda;
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/////
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wire ck_zero_0, clk_s; // intermediate_clk, intermediate_clk_n;
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// Clock frequency = (25 / 2) * 8Mhz
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//
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// Clock period = 10 ns
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// Clock management
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//
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// Generate a usable clock for the rest of the board to run at.
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//
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wire ck_zero_0, clk_s;
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// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
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// Clock period = 12.5 ns
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DCM_SP #(
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DCM_SP #(
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.CLKDV_DIVIDE(2.0),
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.CLKDV_DIVIDE(2.0),
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.CLKFX_DIVIDE(2),
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.CLKFX_DIVIDE(2), // Here's the divide by two
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.CLKFX_MULTIPLY(20),
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.CLKFX_MULTIPLY(20), // and here's the multiply by 20
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.CLKIN_DIVIDE_BY_2("FALSE"),
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.CLKIN_DIVIDE_BY_2("FALSE"),
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.CLKIN_PERIOD(125.0),
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.CLKIN_PERIOD(125.0),
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.CLKOUT_PHASE_SHIFT("NONE"),
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.CLKOUT_PHASE_SHIFT("NONE"),
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.CLK_FEEDBACK("1X"),
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.CLK_FEEDBACK("1X"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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.DLL_FREQUENCY_MODE("LOW"),
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.DLL_FREQUENCY_MODE("LOW"),
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.DUTY_CYCLE_CORRECTION("TRUE"),
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.DUTY_CYCLE_CORRECTION("TRUE"),
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.PHASE_SHIFT(0),
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.PHASE_SHIFT(0),
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.STARTUP_WAIT("TRUE")
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.STARTUP_WAIT("TRUE")
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) u0( .CLKIN(i_clk_8mhz),
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) u0( .CLKIN(i_clk_8mhz),
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.CLK0(ck_zero_0),
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.CLK0(ck_zero_0),
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.CLKFB(ck_zero_0),
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.CLKFB(ck_zero_0),
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.CLKFX(clk_s),
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.CLKFX(clk_s),
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// .CLKFX180(intermediate_clk_n),
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.PSEN(1'b0),
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.PSEN(1'b0),
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.RST(1'b0));
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.RST(1'b0));
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//
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// Generate active-high reset.
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// Generate active-high reset.
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//
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// Actually, we don't. Instead, let this board reset through
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// the reconfiguration/power on process and we never use this
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// wire.
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//
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/*
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/*
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reg r_reset;
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reg r_reset;
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initial r_reset = 1'b1;
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initial r_reset = 1'b1;
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always @(posedge i_clk_12mhz)
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always @(posedge i_clk_12mhz)
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r_reset <= 1'b0;
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r_reset <= 1'b0;
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*/
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*/
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assign reset_s = 1'b0;
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assign reset_s = 1'b0;
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//
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// The UART serial interface
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//
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// Perhaps this should be part of our simulation model as well.
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// For historical reasons, internal to Gisselquist Technology,
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// this has remained separate from the simulation, allowing the
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// simulation to bypass whether or not these two functions work.
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//
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wire rx_stb, tx_stb;
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wire rx_stb, tx_stb;
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wire [7:0] rx_data, tx_data;
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wire [7:0] rx_data, tx_data;
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wire tx_busy;
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wire tx_busy;
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wire [29:0] uart_setup;
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wire [29:0] uart_setup;
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wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
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wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
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assign tx_break = 1'b0;
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assign tx_break = 1'b0;
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rxuart rcvuart(clk_s, reset_s, uart_setup, i_uart, rx_stb, rx_data,
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rxuart rcvuart(clk_s, reset_s, uart_setup,
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i_uart, rx_stb, rx_data,
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rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
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rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
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txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
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txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
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o_uart, tx_busy);
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o_uart, i_uart_cts, tx_busy);
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//
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// BUSMASTER
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//
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// Busmaster is so named because it contains the wishbone
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// interconnect that all of the internal devices are hung off of.
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// To reconfigure this device for another purpose, usually
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// the busmaster module (i.e. the interconnect) is all that needs
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// to be changed: either to add more devices, or to remove them.
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//
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wire [3:0] qspi_dat;
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wire [3:0] qspi_dat;
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wire [1:0] qspi_bmod;
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wire [1:0] qspi_bmod;
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wire [15:0] w_gpio;
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wire [15:0] w_gpio;
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busmaster masterbus(clk_s, reset_s,
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busmaster masterbus(clk_s, reset_s,
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// External ... bus control (if enabled)
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// External ... bus control (if enabled)
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rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
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// SPI/SD-card flash
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// SPI/SD-card flash
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o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
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o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
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// Board lights and switches
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// Board lights and switches
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i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
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i_btn, o_led, o_pwm, { o_pwm_shutdown_n, o_pwm_gain },
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// Keypad connections
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// Keypad connections
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i_kp_row, o_kp_col,
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i_kp_row, o_kp_col,
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// UART control
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// UART control
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uart_setup,
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uart_setup,
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// GPIO lines
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// GPIO lines
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{ i_gpio, io_scl, io_sda }, w_gpio
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{ i_gpio, io_scl, io_sda }, w_gpio
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);
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);
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//
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// Quad SPI support
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//
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// Supporting a Quad SPI port requires knowing which direction the
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// wires are going at each instant, whether the device is in full
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// Quad mode in, full quad mode out, or simply the normal SPI
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// port with one wire in and one wire out. This utilizes our
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// control wires (qspi_bmod) to set the output lines appropriately.
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//
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assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
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assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
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:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
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:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
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//
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// I2C support
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//
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// Supporting I2C requires a couple quick adjustments to our
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// GPIO lines. Specifically, we'll allow that when the output
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// (i.e. w_gpio) pins are high, then the I2C lines float. They
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// will be (need to be) pulled up by a resistor in order to
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// match the I2C protocol, but this change makes them look/act
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// more like GPIO pins.
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//
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assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
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assign io_sda = (w_gpio[0]) ? 1'bz : 1'b0;
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assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
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assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
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assign o_gpio[15:2] = w_gpio[15:2];
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assign o_gpio[15:2] = w_gpio[15:2];
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endmodule
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endmodule
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