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[/] [s6soc/] [trunk/] [rtl/] [wbpwmaudio.v] - Diff between revs 2 and 4

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Line 79... Line 79...
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
module  wbpwmaudio(i_clk,
module  wbpwmaudio(i_clk,
                // Wishbone interface
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                o_pwm, o_int);
                o_pwm, o_aux, o_int);
        parameter       DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @  80MHz
        parameter       DEFAULT_RELOAD = 12'd1814, // about 44.1 kHz @  80MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        //DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
                        NAUX=2, // Dev control values
                        NAUX=2, // Dev control values
                        VARIABLE_RATE=0;
                        VARIABLE_RATE=0,
 
                        TIMING_BITS=12;
        input   i_clk;
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input           i_wb_addr;
        input           i_wb_addr;
        input   [31:0]   i_wb_data;
        input   [31:0]   i_wb_data;
        output  reg             o_wb_ack;
        output  reg             o_wb_ack;
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        // How often shall we create an interrupt?  Every reload_value clocks!
        // How often shall we create an interrupt?  Every reload_value clocks!
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // If VARIABLE_RATE==0, this value will never change and will be kept
        // at the default reload rate (44.1 kHz, for a 100 MHz clock)
        // at the default reload rate (44.1 kHz, for a 100 MHz clock)
 
        wire    [(TIMING_BITS-1):0]      w_reload_value;
        generate
        generate
        if (VARIABLE_RATE != 0)
        if (VARIABLE_RATE != 0)
        begin
        begin
                reg     [31:0]   r_reload_value;
                reg     [(TIMING_BITS-1):0]      r_reload_value;
                initial r_reload_value = DEFAULT_RELOAD;
                initial r_reload_value = DEFAULT_RELOAD;
                always @(posedge i_clk) // Data write
                always @(posedge i_clk) // Data write
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                        if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
                                reload_value <= i_wb_data;
                                r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
                wire    [31:0]   w_reload_value;
 
                assign  w_reload_value = r_reload_value;
                assign  w_reload_value = r_reload_value;
        end else begin
        end else begin
                wire    [31:0]   w_reload_value;
 
                assign  w_reload_value = DEFAULT_RELOAD;
                assign  w_reload_value = DEFAULT_RELOAD;
        end endgenerate
        end endgenerate
 
 
        reg     [31:0]   reload_value, timer;
        reg     [(TIMING_BITS-1):0]      timer;
        initial reload_value = DEFAULT_RELOAD;
 
        initial timer = DEFAULT_RELOAD;
        initial timer = DEFAULT_RELOAD;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                if (timer == 0)
                        timer <= reload_value;
                        timer <= {{(32-TIMING_BITS){1'b0}}, w_reload_value };
                else
                else
                        timer <= timer - 1;
                        timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
 
 
        reg     [15:0]   sample_out;
        reg     [15:0]   sample_out;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (timer == 0)
                if (timer == 0)
                        sample_out <= next_sample;
                        sample_out <= next_sample;
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                                        3'h0, o_int, sample_out };
                                        3'h0, o_int, sample_out };
        end else begin
        end else begin
                reg     [31:0]   r_wb_data;
                reg     [31:0]   r_wb_data;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_wb_addr)
                        if (i_wb_addr)
                                r_wb_data <= reload_value;
                                r_wb_data <= w_reload_value;
                        else
                        else
                                r_wb_data <= { {(12-NAUX){1'b0}}, o_aux,
                                r_wb_data <= { {(12-NAUX){1'b0}}, o_aux,
                                                3'h0, o_int, sample_out };
                                                3'h0, o_int, sample_out };
                assign  o_wb_data = r_wb_data;
                assign  o_wb_data = r_wb_data;
        end endgenerate
        end endgenerate

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