| Line 63... |
Line 63... |
`define WBQSPI_QRD_ADDRESS 6
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`define WBQSPI_QRD_ADDRESS 6
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`define WBQSPI_QRD_DUMMY 7
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`define WBQSPI_QRD_DUMMY 7
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`define WBQSPI_READ_CMD 8
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`define WBQSPI_READ_CMD 8
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`define WBQSPI_READ_DATA 9
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`define WBQSPI_READ_DATA 9
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`define WBQSPI_WAIT_TIL_RDIDLE 10
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`define WBQSPI_WAIT_TIL_RDIDLE 10
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`define WBQSPI_READ_ID_CMD 11
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`define WBQSPI_READ_ID_CMD 11 //
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`define WBQSPI_READ_ID 12
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`define WBQSPI_READ_ID 12 //
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`define WBQSPI_READ_STATUS 13
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`define WBQSPI_READ_STATUS 13 //
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`define WBQSPI_READ_CONFIG 14
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`define WBQSPI_READ_CONFIG 14 //
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`define WBQSPI_WAIT_TIL_IDLE 15
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`define WBQSPI_WAIT_TIL_IDLE 15
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//
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//
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//
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//
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`ifndef READ_ONLY
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`ifndef READ_ONLY
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//
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//
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| Line 145... |
Line 145... |
dirty_sector = 1'b1;
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dirty_sector = 1'b1;
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write_protect = 1'b1;
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write_protect = 1'b1;
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end
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end
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reg [7:0] last_status;
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reg [7:0] last_status;
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reg [9:0] reset_counter;
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reg quad_mode_enabled;
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reg quad_mode_enabled;
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reg spif_cmd, spif_override;
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reg spif_cmd, spif_override;
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reg [(ADDRESS_WIDTH-3):0] spif_addr;
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reg [(ADDRESS_WIDTH-3):0] spif_addr;
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reg [31:0] spif_data;
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reg [31:0] spif_data;
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reg [5:0] state;
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reg [5:0] state;
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reg spif_ctrl, spif_req;
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reg spif_ctrl, spif_req;
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reg alt_cmd, alt_ctrl;
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wire [(ADDRESS_WIDTH-17):0] spif_sector;
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wire [(ADDRESS_WIDTH-17):0] spif_sector;
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assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
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assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
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// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
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// assign o_debug = { spi_wr, spi_spd, spi_hold, state, spi_dbg };
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| Line 163... |
Line 165... |
initial o_wb_stall = 1'b1;
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initial o_wb_stall = 1'b1;
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initial spi_wr = 1'b0;
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initial spi_wr = 1'b0;
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initial spi_len = 2'b00;
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initial spi_len = 2'b00;
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initial quad_mode_enabled = 1'b0;
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initial quad_mode_enabled = 1'b0;
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initial o_interrupt = 1'b0;
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initial o_interrupt = 1'b0;
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initial spif_override = 1'b1;
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always @(posedge i_clk_100mhz)
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always @(posedge i_clk_100mhz)
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begin
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begin
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spif_override <= 1'b0;
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spif_override <= 1'b0;
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alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
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alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
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if (state == `WBQSPI_RESET)
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if (state == `WBQSPI_RESET)
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begin
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begin
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// From a reset, we should
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// From a reset, we should
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// Enable the Quad I/O mode
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// Enable the Quad I/O mode
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// Disable the Write protection bits in the status register
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// Disable the Write protection bits in the status register
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| Line 183... |
Line 188... |
spi_dir <= 1'b0;
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spi_dir <= 1'b0;
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last_status <= 8'h00;
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last_status <= 8'h00;
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state <= `WBQSPI_RESET_QUADMODE;
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state <= `WBQSPI_RESET_QUADMODE;
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spif_req <= 1'b0;
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spif_req <= 1'b0;
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spif_override <= 1'b1;
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spif_override <= 1'b1;
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last_status <= 8'hfc; //
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last_status <= 8'h00; //
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reset_counter <= 10'h3fc; //
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// This guarantees that we aren't starting in quad
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// This guarantees that we aren't starting in quad
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// I/O mode, where the FPGA configuration scripts may
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// I/O mode, where the FPGA configuration scripts may
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// have left us.
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// have left us.
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end else if (state == `WBQSPI_RESET_QUADMODE)
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end else if (state == `WBQSPI_RESET_QUADMODE)
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begin
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begin
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// Okay, so here's the problem: we don't know whether or not
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// Okay, so here's the problem: we don't know whether or not
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// the Xilinx loader started us up in Quad Read I/O idle mode.
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// the Xilinx loader started us up in Quad Read I/O idle mode.
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// So, thus we need to
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// So, thus we need to toggle the clock and CS_n, with fewer
|
|
// clocks than are necessary to transmit a word.
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//
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// Not ready to handle the bus yet, so stall any requests
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// Not ready to handle the bus yet, so stall any requests
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b1;
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o_wb_stall <= 1'b1;
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|
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// Do something ...
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// Do something ...
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if (last_status == 8'h00)
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if (reset_counter == 10'h00)
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begin
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begin
|
spif_override <= 1'b0;
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spif_override <= 1'b0;
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state <= `WBQSPI_IDLE;
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state <= `WBQSPI_IDLE;
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|
|
|
// Find out if we can use Quad I/O mode ...
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state <= `WBQSPI_READ_CONFIG;
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spi_wr <= 1'b1;
|
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spi_len <= 2'b01;
|
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spi_in <= { 8'h35, 24'h00};
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|
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end else begin
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end else begin
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last_status <= last_status - 8'h1;
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reset_counter <= reset_counter - 10'h1;
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spif_override <= 1'b1;
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spif_override <= 1'b1;
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spif_cmd <= last_status[3]; // Toggle CS_n
|
|
spif_ctrl <= last_status[0]; // Toggle clock too
|
|
end
|
end
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end else if (state == `WBQSPI_IDLE)
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end else if (state == `WBQSPI_IDLE)
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begin
|
begin
|
o_interrupt <= 1'b0;
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o_interrupt <= 1'b0;
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o_wb_stall <= 1'b0;
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o_wb_stall <= 1'b0;
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| Line 1182... |
Line 1195... |
end
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end
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end
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end
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end
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end
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|
|
// Command and control during the reset sequence
|
// Command and control during the reset sequence
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assign o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
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assign o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
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assign o_qspi_sck = (spif_override)?spif_ctrl:w_qspi_sck;
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assign o_qspi_sck = (spif_override)?alt_ctrl:w_qspi_sck;
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assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
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assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
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assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
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assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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