| Line 1... |
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbscope.v
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// Filename: wbscope.v
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//
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//
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// Project: FPGA Library of Routines
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// Project: WBScope, a wishbone hosted scope
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//
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//
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// Purpose: This is a generic/library routine for providing a bus accessed
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// Purpose: This is a generic/library routine for providing a bus accessed
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// 'scope' or (perhaps more appropriately) a bus accessed logic
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// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
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// analyzer. The general operation is such that this 'scope' can
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// The general operation is such that this 'scope' can record and report
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// record and report on any 32 bit value transiting through the
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// on any 32 bit value transiting through the FPGA. Once started and
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// FPGA. Once started and reset, the scope records a copy of the
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// reset, the scope records a copy of the input data every time the clock
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// input data every time the clock ticks with the circuit enabled.
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// ticks with the circuit enabled. That is, it records these values up
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// That is, it records these values up until the trigger. Once
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// until the trigger. Once the trigger goes high, the scope will record
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// the trigger goes high, the scope will record for bw_holdoff
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// for bw_holdoff more counts before stopping. Values may then be read
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// more counts before stopping. Values may then be read from the
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// from the buffer, oldest to most recent. After reading, the scope may
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// buffer, oldest to most recent. After reading, the scope may
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// then be reset for another run.
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// then be reset for another run.
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//
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//
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// In general, therefore, operation happens in this fashion:
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// In general, therefore, operation happens in this fashion:
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// 1. A reset is issued.
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// 1. A reset is issued.
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// 2. Recording starts, in a circular buffer, and continues until
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// 2. Recording starts, in a circular buffer, and continues until
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| Line 56... |
Line 55... |
// dw_ A wire/net, controlled by the data clock
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// dw_ A wire/net, controlled by the data clock
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 71... |
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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/////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_interrupt);
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o_interrupt);
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1;
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1,
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DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4),
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HOLDOFFBITS = 20;
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// The input signals that we wish to record
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// The input signals that we wish to record
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input i_clk, i_ce, i_trigger;
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input i_clk, i_ce, i_trigger;
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input [(BUSW-1):0] i_data;
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input [(BUSW-1):0] i_data;
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// The WISHBONE bus for reading and configuring this scope
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// The WISHBONE bus for reading and configuring this scope
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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| Line 106... |
Line 109... |
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// Our status/config register
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// Our status/config register
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wire bw_reset_request, bw_manual_trigger,
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wire bw_reset_request, bw_manual_trigger,
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bw_disable_trigger, bw_reset_complete;
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bw_disable_trigger, bw_reset_complete;
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reg [22:0] br_config;
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reg [22:0] br_config;
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wire [19:0] bw_holdoff;
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wire [(HOLDOFFBITS-1):0] bw_holdoff;
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initial br_config = ((1<<(LGMEM-1))-4);
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initial br_config = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
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if ((i_wb_stb)&&(~i_wb_addr))
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begin
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begin
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if (i_wb_we)
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if (i_wb_we)
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br_config <= { i_wb_data[31],
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br_config <= { i_wb_data[31],
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(i_wb_data[27]),
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(i_wb_data[27]),
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i_wb_data[26],
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i_wb_data[26],
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| Line 121... |
Line 124... |
end else if (bw_reset_complete)
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end else if (bw_reset_complete)
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br_config[22] <= 1'b1;
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br_config[22] <= 1'b1;
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assign bw_reset_request = (~br_config[22]);
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assign bw_reset_request = (~br_config[22]);
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assign bw_manual_trigger = (br_config[21]);
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assign bw_manual_trigger = (br_config[21]);
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assign bw_disable_trigger = (br_config[20]);
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assign bw_disable_trigger = (br_config[20]);
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assign bw_holdoff = br_config[19:0];
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assign bw_holdoff = br_config[(HOLDOFFBITS-1):0];
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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generate
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generate
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if (SYNCHRONOUS > 0)
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if (SYNCHRONOUS > 0)
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begin
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begin
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| Line 133... |
Line 136... |
assign dw_manual_trigger = bw_manual_trigger;
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign bw_reset_complete = bw_reset_request;
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assign bw_reset_complete = bw_reset_request;
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end else begin
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end else begin
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reg r_reset_complete;
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reg r_reset_complete;
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reg [2:0] r_iflags, q_iflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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reg [2:0] r_iflags;
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// Resets are synchronous to the bus clock, not the data clock
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// Resets are synchronous to the bus clock, not the data clock
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// so do a clock transfer here
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// so do a clock transfer here
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initial q_iflags = 3'b000;
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initial q_iflags = 3'b000;
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initial r_reset_complete = 1'b0;
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initial r_reset_complete = 1'b0;
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| Line 150... |
Line 154... |
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assign dw_reset = r_iflags[2];
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assign dw_reset = r_iflags[2];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_disable_trigger = r_iflags[0];
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assign dw_disable_trigger = r_iflags[0];
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reg q_reset_complete, qq_reset_complete;
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(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
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reg qq_reset_complete;
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// Pass an acknowledgement back from the data clock to the bus
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// Pass an acknowledgement back from the data clock to the bus
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// clock that the reset has been accomplished
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// clock that the reset has been accomplished
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initial q_reset_complete = 1'b0;
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initial q_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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| Line 187... |
Line 192... |
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//
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//
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// Determine when memory is full and capture is complete
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// Determine when memory is full and capture is complete
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//
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//
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// Writes take place on the data clock
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// Writes take place on the data clock
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// The counter is unsigned
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(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
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reg less_than_holdoff;
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always @(posedge i_clk)
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if (dw_reset)
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less_than_holdoff <= 1'b1;
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else if (i_ce)
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less_than_holdoff <= (counter < bw_holdoff);
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reg dr_stopped;
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reg dr_stopped;
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reg [19:0] counter; // This is unsigned
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initial dr_stopped = 1'b0;
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initial dr_stopped = 1'b0;
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initial counter = 20'h0000;
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initial counter = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset)
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if (dw_reset)
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begin
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counter <= 0;
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counter <= 0;
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dr_stopped <= 1'b0;
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else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
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end else if ((i_ce)&&(dr_triggered))
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begin // MUST BE a < and not <=, so that we can keep this w/in
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begin // MUST BE a < and not <=, so that we can keep this w/in
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// 20 bits. Else we'd need to add a bit to comparison
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// 20 bits. Else we'd need to add a bit to comparison
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// here.
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// here.
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if (counter < bw_holdoff)
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counter <= counter + 1'b1;
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counter <= counter + 20'h01;
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else
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dr_stopped <= 1'b1;
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end
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end
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always @(posedge i_clk)
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if ((~dr_triggered)||(dw_reset))
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dr_stopped <= 1'b0;
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else if (i_ce)
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dr_stopped <= (counter+1'b1 >= bw_holdoff);
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else
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dr_stopped <= (counter >= bw_holdoff);
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//
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//
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// Actually do our writes to memory. Record, via 'primed' when
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// Actually do our writes to memory. Record, via 'primed' when
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// the memory is full.
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// the memory is full.
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//
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//
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| Line 224... |
Line 239... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset) // For simulation purposes, supply a valid value
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if (dw_reset) // For simulation purposes, supply a valid value
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begin
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begin
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waddr <= 0; // upon reset.
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waddr <= 0; // upon reset.
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dr_primed <= 1'b0;
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dr_primed <= 1'b0;
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end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
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end else if ((i_ce)&&(!dr_stopped))
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begin
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begin
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// mem[waddr] <= i_data;
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// mem[waddr] <= i_data;
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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dr_primed <= (dr_primed)||(&waddr);
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dr_primed <= (dr_primed)||(&waddr);
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
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if ((i_ce)&&(!dr_stopped))
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mem[waddr] <= i_data;
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mem[waddr] <= i_data;
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//
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//
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// Clock transfer of the status signals
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// Clock transfer of the status signals
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//
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//
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| Line 250... |
Line 265... |
// These aren't a problem, since none of these are strobe
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// These aren't a problem, since none of these are strobe
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// signals. They goes from low to high, and then stays high
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// signals. They goes from low to high, and then stays high
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// for many clocks. Swapping is thus easy--two flip flops to
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// for many clocks. Swapping is thus easy--two flip flops to
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// protect against meta-stability and we're done.
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// protect against meta-stability and we're done.
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//
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//
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reg [2:0] q_oflags, r_oflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
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reg [2:0] r_oflags;
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initial q_oflags = 3'h0;
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initial q_oflags = 3'h0;
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initial r_oflags = 3'h0;
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initial r_oflags = 3'h0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if (bw_reset_request)
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if (bw_reset_request)
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begin
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begin
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| Line 272... |
Line 288... |
|
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// Reads use the bus clock
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// Reads use the bus clock
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reg br_wb_ack;
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reg br_wb_ack;
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initial br_wb_ack = 1'b0;
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initial br_wb_ack = 1'b0;
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wire bw_cyc_stb;
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wire bw_cyc_stb;
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assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb));
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assign bw_cyc_stb = (i_wb_stb);
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
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if ((bw_reset_request)
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if ((bw_reset_request)
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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raddr <= 0;
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raddr <= 0;
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else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
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else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
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raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped
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raddr <= raddr + 1'b1; // Data read, when stopped
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|
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if ((bw_cyc_stb)&&(~i_wb_we))
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if ((bw_cyc_stb)&&(~i_wb_we))
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begin // Read from the bus
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begin // Read from the bus
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br_wb_ack <= 1'b1;
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br_wb_ack <= 1'b1;
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end else if ((bw_cyc_stb)&&(i_wb_we))
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end else if ((bw_cyc_stb)&&(i_wb_we))
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| Line 297... |
Line 313... |
always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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nxt_mem <= mem[raddr+waddr+
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nxt_mem <= mem[raddr+waddr+
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(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
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(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
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{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
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{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
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|
|
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wire [19:0] full_holdoff;
|
|
assign full_holdoff[(HOLDOFFBITS-1):0] = bw_holdoff;
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generate if (HOLDOFFBITS < 20)
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assign full_holdoff[19:(HOLDOFFBITS)] = 0;
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endgenerate
|
|
|
wire [4:0] bw_lgmem;
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wire [4:0] bw_lgmem;
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assign bw_lgmem = LGMEM;
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assign bw_lgmem = LGMEM;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if (~i_wb_addr) // Control register read
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if (~i_wb_addr) // Control register read
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o_wb_data <= { bw_reset_request,
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o_wb_data <= { bw_reset_request,
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| Line 309... |
Line 331... |
bw_primed,
|
bw_primed,
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bw_manual_trigger,
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bw_manual_trigger,
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bw_disable_trigger,
|
bw_disable_trigger,
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(raddr == {(LGMEM){1'b0}}),
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(raddr == {(LGMEM){1'b0}}),
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bw_lgmem,
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bw_lgmem,
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bw_holdoff };
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full_holdoff };
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else if (~bw_stopped) // read, prior to stopping
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else if (~bw_stopped) // read, prior to stopping
|
o_wb_data <= i_data;
|
o_wb_data <= i_data;
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else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
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o_wb_data <= nxt_mem; // mem[raddr+waddr];
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o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
