////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbscope.v
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// Filename: wbscope.v
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//
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//
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// Project: WBScope, a wishbone hosted scope
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// Project: WBScope, a wishbone hosted scope
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//
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//
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// Purpose: This is a generic/library routine for providing a bus accessed
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// Purpose: This is a generic/library routine for providing a bus accessed
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// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
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// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
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// The general operation is such that this 'scope' can record and report
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// The general operation is such that this 'scope' can record and report
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// on any 32 bit value transiting through the FPGA. Once started and
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// on any 32 bit value transiting through the FPGA. Once started and
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// reset, the scope records a copy of the input data every time the clock
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// reset, the scope records a copy of the input data every time the clock
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// ticks with the circuit enabled. That is, it records these values up
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// ticks with the circuit enabled. That is, it records these values up
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// until the trigger. Once the trigger goes high, the scope will record
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// until the trigger. Once the trigger goes high, the scope will record
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// for bw_holdoff more counts before stopping. Values may then be read
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// for br_holdoff more counts before stopping. Values may then be read
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// from the buffer, oldest to most recent. After reading, the scope may
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// from the buffer, oldest to most recent. After reading, the scope may
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// then be reset for another run.
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// then be reset for another run.
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//
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//
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// In general, therefore, operation happens in this fashion:
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// In general, therefore, operation happens in this fashion:
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// 1. A reset is issued.
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// 1. A reset is issued.
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// 2. Recording starts, in a circular buffer, and continues until
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// 2. Recording starts, in a circular buffer, and continues until
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// 3. The trigger line is asserted.
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// 3. The trigger line is asserted.
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// The scope registers the asserted trigger by setting
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// The scope registers the asserted trigger by setting
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// the 'o_triggered' output flag.
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// the 'o_triggered' output flag.
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// 4. A counter then ticks until the last value is written
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// 4. A counter then ticks until the last value is written
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// The scope registers that it has stopped recording by
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// The scope registers that it has stopped recording by
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// setting the 'o_stopped' output flag.
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// setting the 'o_stopped' output flag.
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// 5. The scope recording is then paused until the next reset.
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// 5. The scope recording is then paused until the next reset.
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// 6. While stopped, the CPU can read the data from the scope
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// 6. While stopped, the CPU can read the data from the scope
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// 7. -- oldest to most recent
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// 7. -- oldest to most recent
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// 8. -- one value per i_rd&i_clk
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// 8. -- one value per i_rd&i_clk
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// 9. Writes to the data register reset the address to the
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// 9. Writes to the data register reset the address to the
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// beginning of the buffer
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// beginning of the buffer
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//
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//
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// Although the data width DW is parameterized, it is not very changable,
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// Although the data width DW is parameterized, it is not very changable,
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// since the width is tied to the width of the data bus, as is the
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// since the width is tied to the width of the data bus, as is the
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// control word. Therefore changing the data width would require changing
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// control word. Therefore changing the data width would require changing
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// the interface. It's doable, but it would be a change to the interface.
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// the interface. It's doable, but it would be a change to the interface.
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//
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//
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// The SYNCHRONOUS parameter turns on and off meta-stability
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// The SYNCHRONOUS parameter turns on and off meta-stability
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// synchronization. Ideally a wishbone scope able to handle one or two
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// synchronization. Ideally a wishbone scope able to handle one or two
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// clocks would have a changing number of ports as this SYNCHRONOUS
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// clocks would have a changing number of ports as this SYNCHRONOUS
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// parameter changed. Other than running another script to modify
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// parameter changed. Other than running another script to modify
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// this, I don't know how to do that so ... we'll just leave it running
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// this, I don't know how to do that so ... we'll just leave it running
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// off of two clocks or not.
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// off of two clocks or not.
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//
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//
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//
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//
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// Internal to this routine, registers and wires are named with one of the
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// Internal to this routine, registers and wires are named with one of the
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// following prefixes:
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// following prefixes:
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//
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//
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// i_ An input port to the routine
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// i_ An input port to the routine
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// o_ An output port of the routine
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// o_ An output port of the routine
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// br_ A register, controlled by the bus clock
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// br_ A register, controlled by the bus clock
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// dr_ A register, controlled by the data clock
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// dr_ A register, controlled by the data clock
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// bw_ A wire/net, controlled by the bus clock
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// bw_ A wire/net, controlled by the bus clock
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// dw_ A wire/net, controlled by the data clock
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// dw_ A wire/net, controlled by the data clock
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_interrupt);
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o_interrupt);
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1,
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parameter [4:0] LGMEM = 5'd10;
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DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4),
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parameter BUSW = 32;
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HOLDOFFBITS = 20;
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parameter [0:0] SYNCHRONOUS=1;
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parameter HOLDOFFBITS = 20;
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parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
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// The input signals that we wish to record
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// The input signals that we wish to record
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input i_clk, i_ce, i_trigger;
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input i_clk, i_ce, i_trigger;
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input [(BUSW-1):0] i_data;
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input [(BUSW-1):0] i_data;
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// The WISHBONE bus for reading and configuring this scope
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// The WISHBONE bus for reading and configuring this scope
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr; // One address line only
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input i_wb_addr; // One address line only
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input [(BUSW-1):0] i_wb_data;
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input [(BUSW-1):0] i_wb_data;
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output wire o_wb_ack, o_wb_stall;
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output wire o_wb_ack, o_wb_stall;
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output reg [(BUSW-1):0] o_wb_data;
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output reg [(BUSW-1):0] o_wb_data;
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// And, finally, for a final flair --- offer to interrupt the CPU after
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// And, finally, for a final flair --- offer to interrupt the CPU after
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// our trigger has gone off. This line is equivalent to the scope
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// our trigger has gone off. This line is equivalent to the scope
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// being stopped. It is not maskable here.
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// being stopped. It is not maskable here.
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output wire o_interrupt;
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output wire o_interrupt;
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reg [(LGMEM-1):0] raddr;
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reg [(LGMEM-1):0] raddr;
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reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
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reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
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|
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// Our status/config register
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// Our status/config register
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wire bw_reset_request, bw_manual_trigger,
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wire bw_reset_request, bw_manual_trigger,
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bw_disable_trigger, bw_reset_complete;
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bw_disable_trigger, bw_reset_complete;
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reg [22:0] br_config;
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reg [2:0] br_config;
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wire [(HOLDOFFBITS-1):0] bw_holdoff;
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reg [(HOLDOFFBITS-1):0] br_holdoff;
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initial br_config = DEFAULT_HOLDOFF;
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initial br_config = 3'b0;
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initial br_holdoff = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if ((i_wb_stb)&&(~i_wb_addr))
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if ((i_wb_stb)&&(!i_wb_addr))
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begin
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begin
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if (i_wb_we)
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if (i_wb_we)
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begin
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br_config <= { i_wb_data[31],
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br_config <= { i_wb_data[31],
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(i_wb_data[27]),
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i_wb_data[27],
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i_wb_data[26],
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i_wb_data[26] };
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i_wb_data[19:0] };
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br_holdoff = i_wb_data[(HOLDOFFBITS-1):0];
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end
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end else if (bw_reset_complete)
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end else if (bw_reset_complete)
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br_config[22] <= 1'b1;
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br_config[2] <= 1'b1;
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assign bw_reset_request = (~br_config[22]);
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assign bw_reset_request = (!br_config[2]);
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assign bw_manual_trigger = (br_config[21]);
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assign bw_manual_trigger = (br_config[1]);
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assign bw_disable_trigger = (br_config[20]);
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assign bw_disable_trigger = (br_config[0]);
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assign bw_holdoff = br_config[(HOLDOFFBITS-1):0];
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|
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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wire dw_reset, dw_manual_trigger, dw_disable_trigger;
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generate
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generate
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if (SYNCHRONOUS > 0)
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if (SYNCHRONOUS > 0)
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begin
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begin
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assign dw_reset = bw_reset_request;
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assign dw_reset = bw_reset_request;
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign bw_reset_complete = bw_reset_request;
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assign bw_reset_complete = bw_reset_request;
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end else begin
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end else begin
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reg r_reset_complete;
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reg r_reset_complete;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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reg [2:0] r_iflags;
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reg [2:0] r_iflags;
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|
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// Resets are synchronous to the bus clock, not the data clock
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// Resets are synchronous to the bus clock, not the data clock
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// so do a clock transfer here
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// so do a clock transfer here
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initial q_iflags = 3'b000;
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initial q_iflags = 3'b000;
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initial r_reset_complete = 1'b0;
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initial r_reset_complete = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
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q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
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r_iflags <= q_iflags;
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r_iflags <= q_iflags;
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r_reset_complete <= (dw_reset);
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r_reset_complete <= (dw_reset);
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end
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end
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|
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assign dw_reset = r_iflags[2];
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assign dw_reset = r_iflags[2];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_disable_trigger = r_iflags[0];
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assign dw_disable_trigger = r_iflags[0];
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|
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(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
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(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
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reg qq_reset_complete;
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reg qq_reset_complete;
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// Pass an acknowledgement back from the data clock to the bus
|
// Pass an acknowledgement back from the data clock to the bus
|
// clock that the reset has been accomplished
|
// clock that the reset has been accomplished
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initial q_reset_complete = 1'b0;
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initial q_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
|
q_reset_complete <= r_reset_complete;
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q_reset_complete <= r_reset_complete;
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qq_reset_complete <= q_reset_complete;
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qq_reset_complete <= q_reset_complete;
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end
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end
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|
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assign bw_reset_complete = qq_reset_complete;
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assign bw_reset_complete = qq_reset_complete;
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end endgenerate
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end endgenerate
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|
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//
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//
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// Set up the trigger
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// Set up the trigger
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//
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//
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//
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//
|
// Write with the i-clk, or input clock. All outputs read with the
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// Write with the i-clk, or input clock. All outputs read with the
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// WISHBONE-clk, or i_wb_clk clock.
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// WISHBONE-clk, or i_wb_clk clock.
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reg dr_triggered, dr_primed;
|
reg dr_triggered, dr_primed;
|
wire dw_trigger;
|
wire dw_trigger;
|
assign dw_trigger = (dr_primed)&&(
|
assign dw_trigger = (dr_primed)&&(
|
((i_trigger)&&(~dw_disable_trigger))
|
((i_trigger)&&(!dw_disable_trigger))
|
||(dr_triggered)
|
|
||(dw_manual_trigger));
|
||(dw_manual_trigger));
|
initial dr_triggered = 1'b0;
|
initial dr_triggered = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset)
|
if (dw_reset)
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dr_triggered <= 1'b0;
|
dr_triggered <= 1'b0;
|
else if ((i_ce)&&(dw_trigger))
|
else if ((i_ce)&&(dw_trigger))
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dr_triggered <= 1'b1;
|
dr_triggered <= 1'b1;
|
|
|
//
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//
|
// Determine when memory is full and capture is complete
|
// Determine when memory is full and capture is complete
|
//
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//
|
// Writes take place on the data clock
|
// Writes take place on the data clock
|
// The counter is unsigned
|
// The counter is unsigned
|
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
|
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
|
reg less_than_holdoff;
|
|
always @(posedge i_clk)
|
|
if (dw_reset)
|
|
less_than_holdoff <= 1'b1;
|
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else if (i_ce)
|
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less_than_holdoff <= (counter < bw_holdoff);
|
|
|
|
reg dr_stopped;
|
reg dr_stopped;
|
initial dr_stopped = 1'b0;
|
initial dr_stopped = 1'b0;
|
initial counter = 0;
|
initial counter = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset)
|
if (dw_reset)
|
counter <= 0;
|
counter <= 0;
|
else if ((i_ce)&&(dr_triggered)&&(~dr_stopped))
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
// 20 bits. Else we'd need to add a bit to comparison
|
// 20 bits. Else we'd need to add a bit to comparison
|
// here.
|
// here.
|
counter <= counter + 1'b1;
|
counter <= counter + 1'b1;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((~dr_triggered)||(dw_reset))
|
if ((!dr_triggered)||(dw_reset))
|
dr_stopped <= 1'b0;
|
dr_stopped <= 1'b0;
|
else if (i_ce)
|
|
dr_stopped <= (counter+1'b1 >= bw_holdoff);
|
|
else
|
else
|
dr_stopped <= (counter >= bw_holdoff);
|
dr_stopped <= (counter >= br_holdoff);
|
|
|
//
|
//
|
// Actually do our writes to memory. Record, via 'primed' when
|
// Actually do our writes to memory. Record, via 'primed' when
|
// the memory is full.
|
// the memory is full.
|
//
|
//
|
// The 'waddr' address that we are using really crosses two clock
|
// The 'waddr' address that we are using really crosses two clock
|
// domains. While writing and changing, it's in the data clock
|
// domains. While writing and changing, it's in the data clock
|
// domain. Once stopped, it becomes part of the bus clock domain.
|
// domain. Once stopped, it becomes part of the bus clock domain.
|
// The clock transfer on the stopped line handles the clock
|
// The clock transfer on the stopped line handles the clock
|
// transfer for these signals.
|
// transfer for these signals.
|
//
|
//
|
reg [(LGMEM-1):0] waddr;
|
reg [(LGMEM-1):0] waddr;
|
initial waddr = {(LGMEM){1'b0}};
|
initial waddr = {(LGMEM){1'b0}};
|
initial dr_primed = 1'b0;
|
initial dr_primed = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dw_reset) // For simulation purposes, supply a valid value
|
if (dw_reset) // For simulation purposes, supply a valid value
|
begin
|
begin
|
waddr <= 0; // upon reset.
|
waddr <= 0; // upon reset.
|
dr_primed <= 1'b0;
|
dr_primed <= 1'b0;
|
end else if ((i_ce)&&(!dr_stopped))
|
end else if ((i_ce)&&(!dr_stopped))
|
begin
|
begin
|
// mem[waddr] <= i_data;
|
// mem[waddr] <= i_data;
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
dr_primed <= (dr_primed)||(&waddr);
|
dr_primed <= (dr_primed)||(&waddr);
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_ce)&&(!dr_stopped))
|
if ((i_ce)&&(!dr_stopped))
|
mem[waddr] <= i_data;
|
mem[waddr] <= i_data;
|
|
|
//
|
//
|
// Clock transfer of the status signals
|
// Clock transfer of the status signals
|
//
|
//
|
wire bw_stopped, bw_triggered, bw_primed;
|
wire bw_stopped, bw_triggered, bw_primed;
|
generate
|
generate
|
if (SYNCHRONOUS > 0)
|
if (SYNCHRONOUS > 0)
|
begin
|
begin
|
assign bw_stopped = dr_stopped;
|
assign bw_stopped = dr_stopped;
|
assign bw_triggered = dr_triggered;
|
assign bw_triggered = dr_triggered;
|
assign bw_primed = dr_primed;
|
assign bw_primed = dr_primed;
|
end else begin
|
end else begin
|
// These aren't a problem, since none of these are strobe
|
// These aren't a problem, since none of these are strobe
|
// signals. They goes from low to high, and then stays high
|
// signals. They goes from low to high, and then stays high
|
// for many clocks. Swapping is thus easy--two flip flops to
|
// for many clocks. Swapping is thus easy--two flip flops to
|
// protect against meta-stability and we're done.
|
// protect against meta-stability and we're done.
|
//
|
//
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
reg [2:0] r_oflags;
|
reg [2:0] r_oflags;
|
initial q_oflags = 3'h0;
|
initial q_oflags = 3'h0;
|
initial r_oflags = 3'h0;
|
initial r_oflags = 3'h0;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if (bw_reset_request)
|
if (bw_reset_request)
|
begin
|
begin
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q_oflags <= 3'h0;
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q_oflags <= 3'h0;
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r_oflags <= 3'h0;
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r_oflags <= 3'h0;
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end else begin
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end else begin
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q_oflags <= { dr_stopped, dr_triggered, dr_primed };
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q_oflags <= { dr_stopped, dr_triggered, dr_primed };
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r_oflags <= q_oflags;
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r_oflags <= q_oflags;
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end
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end
|
|
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assign bw_stopped = r_oflags[2];
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assign bw_stopped = r_oflags[2];
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assign bw_triggered = r_oflags[1];
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assign bw_triggered = r_oflags[1];
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assign bw_primed = r_oflags[0];
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assign bw_primed = r_oflags[0];
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end endgenerate
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end endgenerate
|
|
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// Reads use the bus clock
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// Reads use the bus clock
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reg br_wb_ack;
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reg br_wb_ack;
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initial br_wb_ack = 1'b0;
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initial br_wb_ack = 1'b0;
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wire bw_cyc_stb;
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wire bw_cyc_stb;
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assign bw_cyc_stb = (i_wb_stb);
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assign bw_cyc_stb = (i_wb_stb);
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
|
begin
|
if ((bw_reset_request)
|
if ((bw_reset_request)
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
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raddr <= 0;
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raddr <= 0;
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else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
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else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
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raddr <= raddr + 1'b1; // Data read, when stopped
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raddr <= raddr + 1'b1; // Data read, when stopped
|
|
|
if ((bw_cyc_stb)&&(~i_wb_we))
|
if ((bw_cyc_stb)&&(!i_wb_we))
|
begin // Read from the bus
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begin // Read from the bus
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br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
// We did this write above
|
// We did this write above
|
br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
br_wb_ack <= 1'b0;
|
br_wb_ack <= 1'b0;
|
end
|
end
|
|
|
reg [31:0] nxt_mem;
|
reg [31:0] nxt_mem;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
nxt_mem <= mem[raddr+waddr+
|
nxt_mem <= mem[raddr+waddr+
|
(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
|
(((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)) ?
|
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
|
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
|
|
|
wire [19:0] full_holdoff;
|
wire [19:0] full_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = bw_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
generate if (HOLDOFFBITS < 20)
|
generate if (HOLDOFFBITS < 20)
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
endgenerate
|
endgenerate
|
|
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if (~i_wb_addr) // Control register read
|
if (!i_wb_addr) // Control register read
|
o_wb_data <= { bw_reset_request,
|
o_wb_data <= { bw_reset_request,
|
bw_stopped,
|
bw_stopped,
|
bw_triggered,
|
bw_triggered,
|
bw_primed,
|
bw_primed,
|
bw_manual_trigger,
|
bw_manual_trigger,
|
bw_disable_trigger,
|
bw_disable_trigger,
|
(raddr == {(LGMEM){1'b0}}),
|
(raddr == {(LGMEM){1'b0}}),
|
bw_lgmem,
|
bw_lgmem,
|
full_holdoff };
|
full_holdoff };
|
else if (~bw_stopped) // read, prior to stopping
|
else if (!bw_stopped) // read, prior to stopping
|
o_wb_data <= i_data;
|
o_wb_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
initial br_level_interrupt = 1'b0;
|
initial br_level_interrupt = 1'b0;
|
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
|
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
&&(~br_level_interrupt);
|
&&(!br_level_interrupt);
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if ((bw_reset_complete)||(bw_reset_request))
|
if ((bw_reset_complete)||(bw_reset_request))
|
br_level_interrupt<= 1'b0;
|
br_level_interrupt<= 1'b0;
|
else
|
else
|
br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
|
|
endmodule
|
endmodule
|
|
|
