URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [hdl/] [vhdl/] [sata_core.vhd] - Diff between revs 7 and 12

Rev 7	Rev 12
Line 159...	Line 159...


`-- USER FIFO DECLARATION`	`-- USER FIFO DECLARATION`
`component user_fifo`	`component user_fifo`
`port (`	`port (`
`clk: IN std_logic;`
`rst: IN std_logic;`	`rst: IN std_logic;`
	`wr_clk: IN std_logic;`
`din: IN std_logic_VECTOR(31 downto 0);`	`din: IN std_logic_VECTOR(31 downto 0);`
`wr_en: IN std_logic;`	`wr_en: IN std_logic;`
	`rd_clk: IN std_logic;`
`rd_en: IN std_logic;`	`rd_en: IN std_logic;`
`dout: OUT std_logic_VECTOR(31 downto 0);`	`dout: OUT std_logic_VECTOR(31 downto 0);`
`full: OUT std_logic;`	`full: OUT std_logic;`
`prog_full: OUT std_logic;`	`prog_full: OUT std_logic;`
`empty: OUT std_logic);`	`empty: OUT std_logic);`
Line 179...	Line 180...

`--- User Logic Fifo for writing data ---`	`--- User Logic Fifo for writing data ---`
`USER_FIFO_i : user_fifo`	`USER_FIFO_i : user_fifo`
`port map (`	`port map (`
`rst => reset,`	`rst => reset,`
`clk => sata_user_clk,`	`wr_clk => SATA_USER_DATA_CLK_IN,`
`din => sata_din,`	`din => sata_din,`
`wr_en => sata_din_we,`	`wr_en => sata_din_we,`
	`rd_clk => sata_user_clk,`
`dout => user_fifo_dout,`	`dout => user_fifo_dout,`
`rd_en => user_din_re,`	`rd_en => user_din_re,`
`full => user_fifo_full,`	`full => user_fifo_full,`
`prog_full => user_fifo_prog_full,`	`prog_full => user_fifo_prog_full,`
`empty => user_fifo_empty);`	`empty => user_fifo_empty);`