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[/] [sata_controller_core/] [trunk/] [sata2_fifo_v1_00_a/] [hdl/] [vhdl/] [sata_link_layer.vhd] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 273... Line 273...
  signal rx_fifo_full      : std_logic;
  signal rx_fifo_full      : std_logic;
  signal rx_fifo_prog_full  : std_logic;
  signal rx_fifo_prog_full  : std_logic;
  signal rx_fifo_din       : std_logic_vector(0 to DATA_WIDTH-1);
  signal rx_fifo_din       : std_logic_vector(0 to DATA_WIDTH-1);
  signal rx_fifo_dout      : std_logic_vector(0 to DATA_WIDTH-1);
  signal rx_fifo_dout      : std_logic_vector(0 to DATA_WIDTH-1);
  signal rx_fifo_data_count      : std_logic_vector(0 to 9);
  signal rx_fifo_data_count      : std_logic_vector(0 to 9);
 
  signal rx_fifo_reset      : std_logic;
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Pre-Scramble Write FIFO from Command Layer
  -- Pre-Scramble Write FIFO from Command Layer
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  signal write_fifo_we        : std_logic;
  signal write_fifo_we        : std_logic;
Line 1185... Line 1186...
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pre-DeScramble RX FIFO from PHY Layer
-- Pre-DeScramble RX FIFO from PHY Layer
---------------------------------------------------------------------------
---------------------------------------------------------------------------
    rx_fifo_din <= rx_datain;
    rx_fifo_din <= rx_datain;
    rx_fifo_re  <= descrambler_din_re_r;
    rx_fifo_re  <= descrambler_din_re_r;
 
    rx_fifo_reset <= sw_reset or descrambler_reset;
 
 
    RX_FIFO : rx_tx_fifo
    RX_FIFO : rx_tx_fifo
        port map (
        port map (
           clk    => sata_user_clk,
           clk    => sata_user_clk,
           rst    => sw_reset,
           rst    => rx_fifo_reset,
           rd_en  => rx_fifo_re,
           rd_en  => rx_fifo_re,
           din    => rx_fifo_din,
           din    => rx_fifo_din,
           wr_en  => rx_fifo_we_next,
           wr_en  => rx_fifo_we_next,
           dout   => rx_fifo_dout,
           dout   => rx_fifo_dout,
           almost_empty  => rx_fifo_almost_empty,
           almost_empty  => rx_fifo_almost_empty,

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