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signal rx_fifo_full : std_logic;
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signal rx_fifo_full : std_logic;
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signal rx_fifo_prog_full : std_logic;
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signal rx_fifo_prog_full : std_logic;
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signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
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signal rx_fifo_data_count : std_logic_vector(0 to 9);
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signal rx_fifo_data_count : std_logic_vector(0 to 9);
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signal rx_fifo_reset : std_logic;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Pre-Scramble Write FIFO from Command Layer
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-- Pre-Scramble Write FIFO from Command Layer
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal write_fifo_we : std_logic;
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signal write_fifo_we : std_logic;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- Pre-DeScramble RX FIFO from PHY Layer
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-- Pre-DeScramble RX FIFO from PHY Layer
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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rx_fifo_din <= rx_datain;
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rx_fifo_din <= rx_datain;
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rx_fifo_re <= descrambler_din_re_r;
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rx_fifo_re <= descrambler_din_re_r;
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rx_fifo_reset <= sw_reset or descrambler_reset;
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RX_FIFO : rx_tx_fifo
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RX_FIFO : rx_tx_fifo
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port map (
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port map (
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clk => sata_user_clk,
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clk => sata_user_clk,
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rst => sw_reset,
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rst => rx_fifo_reset,
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rd_en => rx_fifo_re,
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rd_en => rx_fifo_re,
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din => rx_fifo_din,
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din => rx_fifo_din,
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wr_en => rx_fifo_we_next,
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wr_en => rx_fifo_we_next,
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dout => rx_fifo_dout,
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dout => rx_fifo_dout,
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almost_empty => rx_fifo_almost_empty,
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almost_empty => rx_fifo_almost_empty,
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