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FILES
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FILES
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scan.perl.v
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scan.perl.v
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scan_signal_list.pl
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scan_signal_list.pl
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scan_testbench.perl.v
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scan_testbench.perl.v
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AUTHOR
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AUTHOR
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David Fick - dfick@umich.edu
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David Fick - dfick@umich.edu
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VERSION
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VERSION
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1.0 - June 27, 2010
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1.0 - June 27, 2010
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SCAN DESCRIPTION
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SCAN DESCRIPTION
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This is a simple scan chain implemented with deperlify. It has been
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This is a simple scan chain implemented with deperlify. It has been
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used, successfully, on multiple tapeouts.
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used, successfully, on multiple tapeouts.
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This scan chain is designed to safely and easily move data onto and
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This scan chain is designed to safely and easily move data onto and
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off of a chip with a minimal number of pins. Performance is not a
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off of a chip with a minimal number of pins. Performance is not a
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priority, however, we have found it to be sufficiently fast for
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priority, however, we have found it to be sufficiently fast for
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any student project.
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any student project.
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For safety, this scan uses two non-overlapping "clocks" that operate
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For safety, this scan uses two non-overlapping "clocks" that operate
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out of phase. Each bit in the scan chain has a master latch and
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out of phase. Each bit in the scan chain has a master latch and
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a slave latch. The master latch is connected to the signal "phi",
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a slave latch. The master latch is connected to the signal "phi",
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and the slave latch is connected to the signal "phi_bar". To clock
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and the slave latch is connected to the signal "phi_bar". To clock
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in one bit (and out another), "data_in" is first set to the correct
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in one bit (and out another), "data_in" is first set to the correct
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value, then "phi" is *pulsed*, afterward "phi_bar" is *pulsed*. The
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value, then "phi" is *pulsed*, afterward "phi_bar" is *pulsed*. The
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process then repeats for the next bit. Since each clock is pulsed
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process then repeats for the next bit. Since each clock is pulsed
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individually, they will never overlap. Note that this design
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individually, they will never overlap. Note that this design
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is immune to signal bouncing.
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is immune to signal bouncing.
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Every data_bit coming out of the scan chain unit is first buffered
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Every data_bit coming out of the scan chain unit is first buffered
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with a latch. This latch is transparent when "scan_load_chip" is
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with a latch. This latch is transparent when "scan_load_chip" is
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high. Thus, data is loaded onto the chip by first clocking in all
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high. Thus, data is loaded onto the chip by first clocking in all
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of the data as described above, then pulsing "scan_load_chip".
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of the data as described above, then pulsing "scan_load_chip".
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This means that the signals coming out of the scan unit to the
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This means that the signals coming out of the scan unit to the
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rest of the chip do not toggle randomly when the scan chain is
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rest of the chip do not toggle randomly when the scan chain is
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being loaded, and therefore the scan chain can be operated while
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being loaded, and therefore the scan chain can be operated while
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the chip is running.
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the chip is running.
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The signal "scan_load_chain" controls a mux on the input of each
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The signal "scan_load_chain" controls a mux on the input of each
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latch pair. If "scan_load_chain" is high, then data from the chip
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latch pair. If "scan_load_chain" is high, then data from the chip
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is loaded into the scan chain when the two clocks are pulsed,
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is loaded into the scan chain when the two clocks are pulsed,
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instead of data from the preceding bit. Thus, to read data
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instead of data from the preceding bit. Thus, to read data
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from the chip, first raise "scan_load_chain" high, pulse the two
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from the chip, first raise "scan_load_chain" high, pulse the two
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clocks once as normal, then lower "scan_load_chain". Now that
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clocks once as normal, then lower "scan_load_chain". Now that
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the chip data has been loaded into the scan chain, clock out the
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the chip data has been loaded into the scan chain, clock out the
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data as normal.
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data as normal.
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Due to the buffering latch, complex internal interfaces can be
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Due to the buffering latch, complex internal interfaces can be
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emulated using the scan chain. For instance, an SRAM could be
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emulated using the scan chain. For instance, an SRAM could be
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connected to a clock, chip select, write enable, 64-bit data-in,
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connected to a clock, chip select, write enable, 64-bit data-in,
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and 64-bit data-out, all of which are connected to the scan
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and 64-bit data-out, all of which are connected to the scan
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chain. The scan chain would need to be used a few times for each
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chain. The scan chain would need to be used a few times for each
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"cycle" of the SRAM. For instance, each time the clock signal
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"cycle" of the SRAM. For instance, each time the clock signal
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toggles the scan chain would need to be completely reloaded.
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toggles the scan chain would need to be completely reloaded.
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Although this process is slow, it works reliably.
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Although this process is slow, it works reliably.
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The example description below has additional information about
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The example description below has additional information about
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how to use the scan chain.
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how to use the scan chain.
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EXAMPLE DESCRIPTION
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EXAMPLE DESCRIPTION
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To run the example, use deperlify to generate scan.v and
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To run the example, use deperlify to generate scan.v and
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scan_testbench.v:
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scan_testbench.v:
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perl deperlify.pl scan.perl.v
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perl deperlify.pl scan.perl.v
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perl depeflify.pl scan_testbench.perl.v
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perl depeflify.pl scan_testbench.perl.v
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Then use your Verilog simulator of choice.
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Then use your Verilog simulator of choice.
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This example takes advantage of the DEPERLIFY_INCLUDE command. The
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This example takes advantage of the DEPERLIFY_INCLUDE command. The
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scan.perl.v file reads in the data structure scan_signal_list.pl
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scan.perl.v file reads in the data structure scan_signal_list.pl
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in order to generate the scan chain. The file scan_testbench.perl.v
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in order to generate the scan chain. The file scan_testbench.perl.v
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uses the same data structure to generate variables and functions
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uses the same data structure to generate variables and functions
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to access the scan chain.
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to access the scan chain.
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The testbench generates a write variable and read variable for
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The testbench generates a write variable and read variable for
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each element in the scan chain. The write variable is called
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each element in the scan chain. The write variable is called
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and the read variable is called _read. The values
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and the read variable is called _read. The values
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with the name are what is scanned into the scan chain
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with the name are what is scanned into the scan chain
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by the task "rotate_chain". The task "rotate_chain" writes the
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by the task "rotate_chain". The task "rotate_chain" writes the
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variables with the name _read with the data that is scanned
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variables with the name _read with the data that is scanned
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out by the scan chain. Note that data is simultaneously scanned
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out by the scan chain. Note that data is simultaneously scanned
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in and out.
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in and out.
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To write a value:
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To write a value:
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1. Set the value of to what you desire
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1. Set the value of to what you desire
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2. Call "rotate_chain"
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2. Call "rotate_chain"
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3. Call "load_chip"
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3. Call "load_chip"
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To read a value:
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To read a value:
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1. Call "load_chain"
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1. Call "load_chain"
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2. Call "rotate_chain"
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2. Call "rotate_chain"
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3. Read the value of _read
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3. Read the value of _read
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