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Subversion Repositories scan_based_serial_communication

[/] [scan_based_serial_communication/] [trunk/] [scan.perl.v] - Diff between revs 3 and 4

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Rev 3 Rev 4
Line 74... Line 74...
       # Print scan chain latches
       # Print scan chain latches
       print "   reg [$scan_chain_length-1:0] scan_master;\n";
       print "   reg [$scan_chain_length-1:0] scan_master;\n";
       print "   reg [$scan_chain_length-1:0] scan_slave;\n\n";
       print "   reg [$scan_chain_length-1:0] scan_slave;\n\n";
 
 
       # Print scan_load and scan_next logic
       # Print scan_load and scan_next logic
       print "   wire [$scan_chain_length-1:0] scan_load;\n";
       print "   reg  [$scan_chain_length-1:0] scan_load;\n";
       print "   wire [$scan_chain_length-1:0] scan_next;\n\n";
       print "   wire [$scan_chain_length-1:0] scan_next;\n\n";
 
 
 
       print "   always @ (*) begin\n";
 
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
       for (my $i = 0; $i < scalar @signal_list; $i++) {
 
 
          my $begin = $signal_list[$i]{start};
          my $name      = $signal_list[$i]{name};
          my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
          my $size      = $signal_list[$i]{size};
 
          my $addr_bits = $signal_list[$i]{addr_bits};
 
          my $data_bits = $signal_list[$i]{data_bits};
 
 
 
          my $size_begin = $signal_list[$i]{start};
 
          my $size_end   = $size_begin + $size - 1;
 
 
 
          my $addr_begin = $signal_list[$i]{start};
 
          my $addr_end   = $addr_begin + $addr_bits - 1;
 
 
 
          my $data_begin = $addr_end + 1;
 
          my $data_end   = $data_begin + $data_bits - 1;
 
 
          print "   assign scan_load[$end:$begin] = " . $signal_list[$i]{name} . ";\n";
          if ($signal_list[$i]{addr_bits} == 0) {
 
             print "      scan_load[$size_end:$size_begin] = ${name};\n";
 
          } else {
 
             print "      scan_load[$addr_end:$addr_begin] = scan_slave[$addr_end:$addr_begin];\n";
 
             print "      case (scan_slave[$addr_end:$addr_begin])\n";
 
             for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
 
                print "         ${addr_bits}'d${a}: scan_load[$data_end:$data_begin] = ${name}[$a*$data_bits +: $data_bits];\n";
 
             }
 
             print "      endcase\n";
 
          }
       }
       }
 
 
       print "\n   assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
       print "   end\n\n";
 
 
 
       print "   assign scan_next = scan_load_chain ? scan_load : {scan_data_in, scan_slave[$'$scan_chain_length-1:1]};\n\n";
 
 
       # Print latches
       # Print latches
       print "   //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
       print "   //synopsys one_hot \"scan_phi, scan_phi_bar\"\n";
       print "   always @ (*) begin\n";
       print "   always @ (*) begin\n";
       print "       if (scan_phi)\n";
       print "       if (scan_phi)\n";
Line 97... Line 121...
       print "       if (scan_phi_bar)\n";
       print "       if (scan_phi_bar)\n";
       print "          scan_slave  = scan_master;\n";
       print "          scan_slave  = scan_master;\n";
       print "   end\n\n";
       print "   end\n\n";
 
 
       # Print input latches
       # Print input latches
 
       print "   always @ (*) if (scan_load_chip) begin\n";
 
 
       for (my $i = 0; $i < scalar @signal_list; $i++) {
       for (my $i = 0; $i < scalar @signal_list; $i++) {
          if ($signal_list[$i]{writable} == 1) {
          if ($signal_list[$i]{writable} == 1) {
             my $begin = $signal_list[$i]{start};
 
             my $end   = $signal_list[$i]{start} + $signal_list[$i]{size} - 1;
 
             my $name  = $signal_list[$i]{name};
             my $name  = $signal_list[$i]{name};
             print " always @ (*) if (scan_load_chip) $name = scan_slave[$end:$begin];\n";
             my $size      = $signal_list[$i]{size};
 
             my $addr_bits = $signal_list[$i]{addr_bits};
 
             my $data_bits = $signal_list[$i]{data_bits};
 
 
 
             my $size_begin = $signal_list[$i]{start};
 
             my $size_end   = $size_begin + $size - 1;
 
 
 
             my $addr_begin = $signal_list[$i]{start};
 
             my $addr_end   = $addr_begin + $addr_bits - 1;
 
 
 
             my $data_begin = $addr_end + 1;
 
             my $data_end   = $data_begin + $data_bits - 1;
 
 
 
             if ($signal_list[$i]{addr_bits} == 0) {
 
                print "      $name = scan_slave[$size_end:$size_begin];\n";
 
             } else {
 
                if ($scan_reset_exists) {
 
                   print "      if (scan_slave[$scan_reset_bit]) ${name} = ${size}'d0; else\n";
          }
          }
 
                print "      case (scan_slave[$addr_end:$addr_begin])\n";
 
                for (my $a = 0; ($a+1-1)*$data_bits < $size; $a++) {
 
                   print "         ${addr_bits}'d${a}: ${name}[$a*$data_bits +: $data_bits] = scan_slave[$data_end:$data_begin];\n";
       }
       }
 
                print "      endcase\n";
 
             }
 
          }
 
       }
 
 
 
       print "   end\n\n";
 
 
       # Print data_out
       # Print data_out
       print "   assign scan_data_out = scan_slave[0];\n";
       print "   assign scan_data_out = scan_slave[0];\n";
 
 
       */
       */

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