| Line 20... |
Line 20... |
{ size => 1, writable => 1, name => 'w1_r0'},
|
{ size => 1, writable => 1, name => 'w1_r0'},
|
|
|
|
|
|
|
{ size => 1, writable => 1, name => 'write_data_1'},
|
{ size => 1, writable => 1, name => 'write_data_1'},
|
{ size => 2, writable => 1, name => 'write_data_2'},
|
{ size => 2, writable => 1, name => 'write_data_2', reset => 3},
|
{ size => 3, writable => 1, name => 'write_data_3'},
|
{ size => 3, writable => 1, name => 'write_data_3'},
|
|
|
{ size => 16, writable => 1, name => 'write_data_array', addr_bits => 2, data_bits => 4},
|
{ size => 16, writable => 1, name => 'write_data_array', addr_bits => 2, data_bits => 4, reset => 0xAA55},
|
|
|
# Outputs - chip to outside
|
# Outputs - chip to outside
|
{ size => 1, writable => 0, name => 'read_data_1'},
|
{ size => 1, writable => 0, name => 'read_data_1'},
|
{ size => 2, writable => 0, name => 'read_data_2'},
|
{ size => 2, writable => 0, name => 'read_data_2'},
|
{ size => 3, writable => 0, name => 'read_data_3'},
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{ size => 3, writable => 0, name => 'read_data_3'},
|
