| Line 138... |
Line 138... |
$display("Contents of Mem after reading data file:");
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$display("Contents of Mem after reading data file:");
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for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
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for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);
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end
|
end
|
reg qCmd;
|
reg qCmd;
|
reg [2:0] crcCnt;
|
reg [2:0] crcCnt;
|
|
|
|
reg add_wrong_cmd_crc;
|
|
reg add_wrong_cmd_indx;
|
|
reg add_wrong_data_crc;
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|
|
initial begin
|
initial begin
|
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add_wrong_data_crc<=0;
|
|
add_wrong_cmd_indx<=0;
|
|
add_wrong_cmd_crc<=0;
|
cardIdentificationState<=1;
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cardIdentificationState<=1;
|
state<=IDLE;
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state<=IDLE;
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dataState<=DATA_IDLE;
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dataState<=DATA_IDLE;
|
Busy<=0;
|
Busy<=0;
|
oeCmd<=0;
|
oeCmd<=0;
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| Line 383... |
Line 391... |
ResetCard;
|
ResetCard;
|
end
|
end
|
2 : begin
|
2 : begin
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if (lastCMD != 41 && outDelayCnt==0) begin
|
if (lastCMD != 41 && outDelayCnt==0) begin
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
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//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;
|
CardStatus[3]<=1;
|
CardStatus[3]<=1;
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end
|
end
|
response_CMD[127:8] <= CID;
|
response_CMD[127:8] <= CID;
|
appendCrc<=0;
|
appendCrc<=0;
|
CardStatus[12:9] <=2;
|
CardStatus[12:9] <=2;
|
end
|
end
|
3 : begin
|
3 : begin
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if (lastCMD != 2 && outDelayCnt==0 ) begin
|
if (lastCMD != 2 && outDelayCnt==0 ) begin
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
$fdisplay(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
//$display(sdModel_file_desc, "**Error in sequnce, CMD 2 should precede 3 in Startup state") ;
|
CardStatus[3]<=1;
|
CardStatus[3]<=1;
|
end
|
end
|
response_CMD[127:112] <= RCA[15:0] ;
|
response_CMD[127:112] <= RCA[15:0] ;
|
response_CMD[111:96] <= CardStatus[15:0] ;
|
response_CMD[111:96] <= CardStatus[15:0] ;
|
appendCrc<=1;
|
appendCrc<=1;
|
| Line 418... |
Line 426... |
end
|
end
|
else if (outDelayCnt==0)begin
|
else if (outDelayCnt==0)begin
|
response_CMD <= 0;
|
response_CMD <= 0;
|
response_S<=0;
|
response_S<=0;
|
$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
$fdisplay(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
$display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
// $display(sdModel_file_desc, "**Error Invalid CMD, %h",inCmd[45:40]) ;
|
end
|
end
|
end
|
end
|
7: begin
|
7: begin
|
if (outDelayCnt==0) begin
|
if (outDelayCnt==0) begin
|
if (inCmd[39:24]== RCA[15:0]) begin
|
if (inCmd[39:24]== RCA[15:0]) begin
|
| Line 518... |
Line 526... |
oeCmd<=1;
|
oeCmd<=1;
|
cmdOut<=1;
|
cmdOut<=1;
|
response_CMD[135:134] <=0;
|
response_CMD[135:134] <=0;
|
|
|
if (responseType != 3)
|
if (responseType != 3)
|
|
if (!add_wrong_cmd_indx)
|
response_CMD[133:128] <=inCmd[45:40];
|
response_CMD[133:128] <=inCmd[45:40];
|
|
else
|
|
response_CMD[133:128] <=0;
|
|
|
if (responseType == 3)
|
if (responseType == 3)
|
response_CMD[133:128] <=6'b111111;
|
response_CMD[133:128] <=6'b111111;
|
|
|
lastCMD <=inCmd[45:40];
|
lastCMD <=inCmd[45:40];
|
end
|
end
|
| Line 551... |
Line 563... |
if (cmdWrite >= response_S-9)
|
if (cmdWrite >= response_S-9)
|
crcEn<=0;
|
crcEn<=0;
|
end
|
end
|
else if (cmdWrite!=0) begin
|
else if (cmdWrite!=0) begin
|
crcEn<=0;
|
crcEn<=0;
|
|
if (add_wrong_cmd_crc) begin
|
|
cmdOut<=0;
|
|
crcCnt<=crcCnt+1;
|
|
end
|
|
else begin
|
cmdOut<=crcOut[6-crcCnt];
|
cmdOut<=crcOut[6-crcCnt];
|
crcCnt<=crcCnt+1;
|
crcCnt<=crcCnt+1;
|
if (responseType == 3)
|
if (responseType == 3)
|
cmdOut<=1;
|
cmdOut<=1;
|
end
|
end
|
|
end
|
if (cmdWrite == response_S-1)
|
if (cmdWrite == response_S-1)
|
cmdOut<=1;
|
cmdOut<=1;
|
|
|
end
|
end
|
endcase
|
endcase
|
| Line 598... |
Line 616... |
if (wptr)
|
if (wptr)
|
Inbuff[block_cnt][7:4] <= dat;
|
Inbuff[block_cnt][7:4] <= dat;
|
else
|
else
|
Inbuff[block_cnt][3:0] <= dat;
|
Inbuff[block_cnt][3:0] <= dat;
|
|
|
|
if (!add_wrong_data_crc)
|
crcDat_in<=dat;
|
crcDat_in<=dat;
|
|
else
|
|
crcDat_in<=4'b1010;
|
|
|
crc_ok<=1;
|
crc_ok<=1;
|
transf_cnt<=transf_cnt+1;
|
transf_cnt<=transf_cnt+1;
|
if (wptr)
|
if (wptr)
|
block_cnt<=block_cnt+1;
|
block_cnt<=block_cnt+1;
|
wptr<=~wptr;
|
wptr<=~wptr;
|
| Line 691... |
Line 713... |
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][7:4];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][7:4];
|
end
|
end
|
else begin
|
else begin
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
|
last_din<=FLASHmem[BlockAddr+(write_out_index)][3:0];
|
|
if (!add_wrong_data_crc)
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
|
crcDat_in<= FLASHmem[BlockAddr+(write_out_index)][3:0];
|
|
else
|
|
crcDat_in<=4'b1010;
|
write_out_index<=write_out_index+1;
|
write_out_index<=write_out_index+1;
|
|
|
end
|
end
|
|
|
|
|
datOut<= last_din;
|
datOut<= last_din;
|
|
|
|
|
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
|
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
|
crcDat_en<=0;
|
crcDat_en<=0;
|
| Line 779... |
Line 806... |
end
|
end
|
end
|
end
|
|
|
task ResetCard; // MAC registers
|
task ResetCard; // MAC registers
|
begin
|
begin
|
|
add_wrong_data_crc<=0;
|
|
add_wrong_cmd_indx<=0;
|
|
add_wrong_cmd_crc<=0;
|
cardIdentificationState<=1;
|
cardIdentificationState<=1;
|
state<=IDLE;
|
state<=IDLE;
|
dataState<=DATA_IDLE;
|
dataState<=DATA_IDLE;
|
Busy<=0;
|
Busy<=0;
|
oeCmd<=0;
|
oeCmd<=0;
|
