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Subversion Repositories sdcard_mass_storage_controller

[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Diff between revs 127 and 135

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Rev 127	Rev 135
Line 1...	Line 1...
//`include "timescale.v"	//`include "timescale.v"
`include "SD_defines.v"	`include "sd_defines.v"
`define tTLH 10 //Clock rise time	`define tTLH 10 //Clock rise time
`define tHL 10 //Clock fall time	`define tHL 10 //Clock fall time
`define tISU 6 //Input setup time	`define tISU 6 //Input setup time
`define tIH 0 //Input hold time	`define tIH 0 //Input hold time
`define tODL 14 //Output delay	`define tODL 14 //Output delay
`define DLY_TO_OUTP 47	`define DLY_TO_OUTP 47

`define BLOCKSIZE 512	`define BLOCKSIZE 512
`define MEMSIZE 2048 // 4 block	`define MEMSIZE 24643590 // 2mb block
`define BLOCK_BUFFER_SIZE 1	`define BLOCK_BUFFER_SIZE 1
`define TIME_BUSY 64	`define TIME_BUSY 63

`define PRG 7	`define PRG 7
`define RCV 6	`define RCV 6
`define DATAS 5	`define DATAS 5
`define TRAN 4	`define TRAN 4
Line 54...	Line 54...
`reg crcRst;`	`reg crcRst;`
`reg [31:0] CardStatus;`	`reg [31:0] CardStatus;`
`reg [15:0] RCA;`	`reg [15:0] RCA;`
`reg [31:0] OCR;`	`reg [31:0] OCR;`
`reg [120:0] CID;`	`reg [120:0] CID;`
	`reg [120:0] CSD;`
`reg Busy; //0 when busy`	`reg Busy; //0 when busy`
`wire [6:0] crcOut;`	`wire [6:0] crcOut;`
`reg [4:0] crc_c;`	`reg [4:0] crc_c;`

`reg [3:0] CurrentState;`	`reg [3:0] CurrentState;`
`reg [3:0] DataCurrentState;`	`reg [3:0] DataCurrentState;`
`define RCASTART 16'h20	`define RCASTART 16'h2000
`define OCRSTART 32'hff8000	`define OCRSTART 32'hff8000
`define STATUSSTART 32'h0	`define STATUSSTART 32'h0
`define CIDSTART 128'h00ffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway	`define CIDSTART 128'hffffffddddddddaaaaaaaa99999999 //Just some random data not really usefull anyway
	`define CSDSTART 128'hadaeeeddddddddaaaaaaaa12345678

`define outDelay 4	`define outDelay 4
`reg [2:0] outDelayCnt;`	`reg [2:0] outDelayCnt;`
`reg [9:0] flash_write_cnt;`	`reg [9:0] flash_write_cnt;`
`reg [8:0] flash_blockwrite_cnt;`	`reg [8:0] flash_blockwrite_cnt;`
Line 106...	Line 108...
`reg [3:0] last_din;`	`reg [3:0] last_din;`



`reg crcDat_rst;`	`reg crcDat_rst;`
	`reg mult_read;`
	`reg mult_write;`
`reg crcDat_en;`	`reg crcDat_en;`
`reg [3:0] crcDat_in;`	`reg [3:0] crcDat_in;`
`wire [15:0] crcDat_out [3:0];`	`wire [15:0] crcDat_out [3:0];`

`genvar i;`	`genvar i;`
`generate`	`generate`
`for(i=0; i<4; i=i+1) begin:CRC_16_gen`	`for(i=0; i<4; i=i+1) begin:CRC_16_gen`
`SD_CRC_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);`	`sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);`
`end`	`end`
`endgenerate`	`endgenerate`
`SD_CRC_7 CRC_7(`	`sd_crc_7 crc_7(`
`crcIn,`	`crcIn,`
`crcEn,`	`crcEn,`
`sdClk,`	`sdClk,`
`crcRst,`	`crcRst,`
`crcOut);`	`crcOut);`

	`reg stop;`

`reg appendCrc;`	`reg appendCrc;`
`reg [5:0] startUppCnt;`	`reg [5:0] startUppCnt;`

`reg q_start_bit;`	`reg q_start_bit;`
`//Card initinCMd`	`//Card initinCMd`
`initial $readmemh("../bin/FLASH.txt",FLASHmem);`	`initial $readmemh("../bin/ramdisk2.hex",FLASHmem);`

`integer k;`	`integer k;`
`initial begin`	`initial begin`
`$display("Contents of Mem after reading data file:");`	`$display("Contents of Mem after reading data file:");`
`for (k=0; k<10; k=k+1) $display("%d:%h",k,FLASHmem[k]);`	`for (k=0; k<512; k=k+1) $display("%d:%h",k,FLASHmem[k]);`
`end`	`end`
`reg qCmd;`	`reg qCmd;`
`reg [2:0] crcCnt;`	`reg [2:0] crcCnt;`

`reg add_wrong_cmd_crc;`	`reg add_wrong_cmd_crc;`
Line 147...	Line 152...

`initial begin`	`initial begin`
`add_wrong_data_crc<=0;`	`add_wrong_data_crc<=0;`
`add_wrong_cmd_indx<=0;`	`add_wrong_cmd_indx<=0;`
`add_wrong_cmd_crc<=0;`	`add_wrong_cmd_crc<=0;`
	`stop<=1;`
`cardIdentificationState<=1;`	`cardIdentificationState<=1;`
`state<=IDLE;`	`state<=IDLE;`
`dataState<=DATA_IDLE;`	`dataState<=DATA_IDLE;`
`Busy<=0;`	`Busy<=0;`
`oeCmd<=0;`	`oeCmd<=0;`
Line 163...	Line 169...
`InbuffStatus<=0;`	`InbuffStatus<=0;`
`datOut<=0;`	`datOut<=0;`
`inCmd<=0;`	`inCmd<=0;`
`BusWidth<=1;`	`BusWidth<=1;`
`responseType=0;`	`responseType=0;`
	`mult_read=0;`
	`mult_write=0;`
`crcIn<=0;`	`crcIn<=0;`
`response_S<=0;`	`response_S<=0;`
`crcEn<=0;`	`crcEn<=0;`
`crcRst<=0;`	`crcRst<=0;`
`cmdRead<=0;`	`cmdRead<=0;`
Line 175...	Line 183...
`appendCrc<=0;`	`appendCrc<=0;`
RCA<= `RCASTART;	RCA<= `RCASTART;
OCR<= `OCRSTART;	OCR<= `OCRSTART;
CardStatus <= `STATUSSTART;	CardStatus <= `STATUSSTART;
CID<=`CIDSTART;	CID<=`CIDSTART;
	CSD<=`CSDSTART;
`response_CMD<=0;`	`response_CMD<=0;`
`outDelayCnt<=0;`	`outDelayCnt<=0;`
`crcDat_rst<=1;`	`crcDat_rst<=1;`
`crcDat_en<=0;`	`crcDat_en<=0;`
`crcDat_in<=0;`	`crcDat_in<=0;`
Line 189...	Line 198...
`transf_cnt<=0;`	`transf_cnt<=0;`
`crcDat_rst<=1;`	`crcDat_rst<=1;`
`crcDat_en<=0;`	`crcDat_en<=0;`
`crcDat_in<=0;`	`crcDat_in<=0;`
`flash_write_cnt<=0;`	`flash_write_cnt<=0;`
	`startUppCnt<=0;`
`flash_blockwrite_cnt<=0;`	`flash_blockwrite_cnt<=0;`
`end`	`end`

`//CARD logic`	`//CARD logic`

Line 235...	Line 245...
`always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )`	`always @ (dataState or CardStatus or crc_c or flash_write_cnt or dat[0] )`
`begin : FSM_COMBODAT`	`begin : FSM_COMBODAT`
`next_datastate = 0;`	`next_datastate = 0;`
`case(dataState)`	`case(dataState)`
`DATA_IDLE: begin`	`DATA_IDLE: begin`
if (CardStatus[12:9]==`RCV )	if ((CardStatus[12:9]==`RCV) \|\| (mult_write == 1'b1) )
`next_datastate = READ_WAITS;`	`next_datastate = READ_WAITS;`
else if (CardStatus[12:9]==`DATAS )	else if ((CardStatus[12:9]==`DATAS )\|\| (mult_read == 1'b1) )
`next_datastate = WRITE_DATA;`	`next_datastate = WRITE_DATA;`
`else`	`else`
`next_datastate = DATA_IDLE;`	`next_datastate = DATA_IDLE;`
`end`	`end`

Line 253...	Line 263...
`end`	`end`

`READ_DATA : begin`	`READ_DATA : begin`
`if (crc_c==0 )`	`if (crc_c==0 )`
`next_datastate = WRITE_FLASH;`	`next_datastate = WRITE_FLASH;`
`else`	`else begin`
	`if (stop == 1'b0)`
`next_datastate = READ_DATA;`	`next_datastate = READ_DATA;`
	`else`
	`next_datastate = DATA_IDLE;`
	`end`


`end`	`end`
`WRITE_FLASH : begin`	`WRITE_FLASH : begin`
`if (flash_write_cnt>265 )`	`if (flash_write_cnt>265 )`
`next_datastate = DATA_IDLE;`	`next_datastate = DATA_IDLE;`
`else`	`else`
`next_datastate = WRITE_FLASH;`	`next_datastate = WRITE_FLASH;`

`end`	`end`

`WRITE_DATA : begin`	`WRITE_DATA : begin`
if (transf_cnt >= `BIT_BLOCK)	if (transf_cnt >= `BIT_BLOCK)
`next_datastate= DATA_IDLE;`	`next_datastate= DATA_IDLE;`
`else`	`else`
	`begin`
	`if (stop == 1'b0)`
`next_datastate=WRITE_DATA;`	`next_datastate=WRITE_DATA;`
	`else`
	`next_datastate = DATA_IDLE;`
	`end`
`end`	`end`




Line 302...	Line 325...
`CardStatus[8]<=1;`	`CardStatus[8]<=1;`
`else`	`else`
`CardStatus[8]<=0;`	`CardStatus[8]<=0;`
`end`	`end`
`else`	`else`
`CardStatus[8]<=0;`	`CardStatus[8]<=1;`

`startUppCnt<=startUppCnt+1;`	`startUppCnt<=startUppCnt+1;`
`OCR[31]<=Busy;`	`OCR[31]<=Busy;`
if (startUppCnt == `TIME_BUSY)	if (startUppCnt == `TIME_BUSY)
`Busy <=1;`	`Busy <=1;`
Line 319...	Line 342...

`//read data and cmd on rising edge`	`//read data and cmd on rising edge`
`always @ (posedge sdClk) begin`	`always @ (posedge sdClk) begin`
`case(state)`	`case(state)`
`IDLE: begin`	`IDLE: begin`
	`mult_write <= 0;`
	`mult_read <=0;`
`crcIn<=0;`	`crcIn<=0;`
`crcEn<=0;`	`crcEn<=0;`
`crcRst<=1;`	`crcRst<=1;`
`oeCmd<=0;`	`oeCmd<=0;`
	`stop<=0;`
`cmdRead<=0;`	`cmdRead<=0;`
`appendCrc<=0;`	`appendCrc<=0;`
`ValidCmd<=0;`	`ValidCmd<=0;`
`inValidCmd=0;`	`inValidCmd=0;`
`cmdWrite<=0;`	`cmdWrite<=0;`
Line 374...	Line 398...
`0 : response_S <= 0;`	`0 : response_S <= 0;`
`2 : response_S <= 136;`	`2 : response_S <= 136;`
`3 : response_S <= 48;`	`3 : response_S <= 48;`
`7 : response_S <= 48;`	`7 : response_S <= 48;`
`8 : response_S <= 0;`	`8 : response_S <= 0;`
	`9 : response_S <= 136;`
`14 : response_S <= 0;`	`14 : response_S <= 0;`
`16 : response_S <= 48;`	`16 : response_S <= 48;`
`17 : response_S <= 48;`	`17 : response_S <= 48;`
	`18 : response_S <= 48;`
`24 : response_S <= 48;`	`24 : response_S <= 48;`
	`25 : response_S <= 48;`
`33 : response_S <= 48;`	`33 : response_S <= 48;`
`55 : response_S <= 48;`	`55 : response_S <= 48;`
`41 : response_S <= 48;`	`41 : response_S <= 48;`
`endcase`	`endcase`
`case(inCmd[45:40])`	`case(inCmd[45:40])`
Line 444...	Line 471...
`CardStatus[12:9] <=3;`	`CardStatus[12:9] <=3;`
`end`	`end`
`end`	`end`
`end`	`end`
`8 : response_CMD[127:96] <= 0; //V1.0 card`	`8 : response_CMD[127:96] <= 0; //V1.0 card`

	`9 : begin`
	`if (lastCMD != 41 && outDelayCnt==0) begin`
	`$fdisplay(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
	`//$display(sdModel_file_desc, "**Error in sequnce, ACMD 41 should precede 2 in Startup state") ;`
	`CardStatus[3]<=1;`
	`end`
	`response_CMD[127:8] <= CSD;`
	`appendCrc<=0;`
	`CardStatus[12:9] <=2;`
	`end`

	`12: begin`
	`response_CMD[127:96] <= CardStatus ;`
	`stop<=1;`
	`mult_write <= 0;`
	`mult_read <=0;`
	CardStatus[12:9] <= `TRAN;
	`end`


`16 : begin`	`16 : begin`
`response_CMD[127:96] <= CardStatus ;`	`response_CMD[127:96] <= CardStatus ;`

`end`	`end`





`17 : begin`	`17 : begin`
`if (outDelayCnt==0) begin`	`if (outDelayCnt==0) begin`
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate	if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
CardStatus[12:9] <=`DATAS;//Put card in data state	CardStatus[12:9] <=`DATAS;//Put card in data state
`response_CMD[127:96] <= CardStatus ;`	`response_CMD[127:96] <= CardStatus ;`
Line 465...	Line 518...
`end`	`end`
`end`	`end`

`end`	`end`

	`18 : begin`
	`if (outDelayCnt==0) begin`
	if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
	CardStatus[12:9] <=`DATAS;//Put card in data state
	`response_CMD[127:96] <= CardStatus ;`
	`mult_read <= 1;`
	`BlockAddr = inCmd[39:8];`
	`if (BlockAddr%512 !=0)`
	`$display("**Block Misalign Error");`
	`end`
	`else begin`
	`response_S <= 0;`
	`response_CMD[127:96] <= 0;`

	`end`
	`end`

	`end`

`24 : begin`	`24 : begin`
`if (outDelayCnt==0) begin`	`if (outDelayCnt==0) begin`
if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate	if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
`if (CardStatus[8]) begin //If Free write buffer`	`if (CardStatus[8]) begin //If Free write buffer`
CardStatus[12:9] <=`RCV;//Put card in Rcv state	CardStatus[12:9] <=`RCV;//Put card in Rcv state
Line 486...	Line 558...
`else begin`	`else begin`
`response_S <= 0;`	`response_S <= 0;`
`response_CMD[127:96] <= 0;`	`response_CMD[127:96] <= 0;`
`end`	`end`
`end`	`end`

`end`	`end`
	`25 : begin`
	`if (outDelayCnt==0) begin`
	if (CardStatus[12:9] == `TRAN) begin //If card is in transferstate
	`if (CardStatus[8]) begin //If Free write buffer`
	CardStatus[12:9] <=`RCV;//Put card in Rcv state
	`response_CMD[127:96] <= CardStatus ;`
	`BlockAddr = inCmd[39:8];`
	`mult_write <= 1;`
	`if (BlockAddr%512 !=0)`
	`$display("**Block Misalign Error");`
	`end`
	`else begin`
	`response_CMD[127:96] <= CardStatus;`
	`$fdisplay(sdModel_file_desc, "**Error Try to blockwrite when No Free Writebuffer") ;`
	`$display("**Error Try to blockwrite when No Free Writebuffer") ;`
	`end`
	`end`
	`else begin`
	`response_S <= 0;`
	`response_CMD[127:96] <= 0;`
	`end`
	`end`
	`end`

`33 : response_CMD[127:96] <= 48;`	`33 : response_CMD[127:96] <= 48;`
`55 :`	`55 :`
`begin`	`begin`
`response_CMD[127:96] <= CardStatus ;`	`response_CMD[127:96] <= CardStatus ;`
`CardStatus[5] <=1; //Next CMD is AP specific CMD`	`CardStatus[5] <=1; //Next CMD is AP specific CMD`
Line 596...	Line 691...
`always @ (posedge sdClk) begin`	`always @ (posedge sdClk) begin`

`case (dataState)`	`case (dataState)`
`DATA_IDLE: begin`	`DATA_IDLE: begin`

	`crcDat_rst<=1;`
	`crcDat_en<=0;`
	`crcDat_in<=0;`

`end`	`end`

`READ_WAITS: begin`	`READ_WAITS: begin`
`oeDat<=0;`	`oeDat<=0;`
`crcDat_rst<=0;`	`crcDat_rst<=0;`
Line 612...	Line 711...


`InbuffStatus<=1;`	`InbuffStatus<=1;`
if (transf_cnt<`BIT_BLOCK_REC) begin	if (transf_cnt<`BIT_BLOCK_REC) begin
`if (wptr)`	`if (wptr)`
`Inbuff[block_cnt][7:4] <= dat;`
`else`
`Inbuff[block_cnt][3:0] <= dat;`	`Inbuff[block_cnt][3:0] <= dat;`
	`else`
	`Inbuff[block_cnt][7:4] <= dat;`

`if (!add_wrong_data_crc)`	`if (!add_wrong_data_crc)`
`crcDat_in<=dat;`	`crcDat_in<=dat;`
`else`	`else`
`crcDat_in<=4'b1010;`	`crcDat_in<=4'b1010;`
Line 677...	Line 776...
`DATA_IDLE: begin`	`DATA_IDLE: begin`
`write_out_index<=0;`	`write_out_index<=0;`
`transf_cnt<=0;`	`transf_cnt<=0;`
`data_send_index<=0;`	`data_send_index<=0;`
`outdly_cnt<=0;`	`outdly_cnt<=0;`
	`flash_write_cnt<=0;`
`end`	`end`


`WRITE_DATA: begin`	`WRITE_DATA: begin`
`oeDat<=1;`	`oeDat<=1;`
Line 782...	Line 881...
`datOut[0]<=0;`	`datOut[0]<=0;`

`flash_blockwrite_cnt<=flash_blockwrite_cnt+2;`	`flash_blockwrite_cnt<=flash_blockwrite_cnt+2;`
`FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];`	`FLASHmem[BlockAddr+(flash_blockwrite_cnt)]<=Inbuff[flash_blockwrite_cnt];`
`FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];`	`FLASHmem[BlockAddr+(flash_blockwrite_cnt+1)]<=Inbuff[flash_blockwrite_cnt+1];`

`end`	`end`
`else begin`	`else begin`
`datOut<=1;`	`datOut<=1;`
`InbuffStatus<=0;`	`InbuffStatus<=0;`
CardStatus[12:9] <= `TRAN;	CardStatus[12:9] <= `TRAN;
Line 796...	Line 896...

`integer sdModel_file_desc;`	`integer sdModel_file_desc;`

`initial`	`initial`
`begin`	`begin`
`sdModel_file_desc = $fopen("../log/sd_model.log");`	`sdModel_file_desc = $fopen("../out/sd_model.log");`
`if (sdModel_file_desc < 2)`	`if (sdModel_file_desc < 2)`
`begin`	`begin`
`$display("*E Could not open/create testbench log file in /log/ directory!");`	`$display("*E Could not open/create testbench log file in /log/ directory!");`
`$finish;`	`$finish;`
`end`	`end`
Line 820...	Line 920...
`CardTransferActive<=0;`	`CardTransferActive<=0;`
`qCmd<=1;`	`qCmd<=1;`
`oeDat<=0;`	`oeDat<=0;`
`cmdOut<=0;`	`cmdOut<=0;`
`cmdWrite<=0;`	`cmdWrite<=0;`
	`startUppCnt<=0;`
`InbuffStatus<=0;`	`InbuffStatus<=0;`
`datOut<=0;`	`datOut<=0;`
`inCmd<=0;`	`inCmd<=0;`
`BusWidth<=1;`	`BusWidth<=1;`
`responseType=0;`	`responseType=0;`
Line 838...	Line 938...
`appendCrc<=0;`	`appendCrc<=0;`
RCA<= `RCASTART;	RCA<= `RCASTART;
OCR<= `OCRSTART;	OCR<= `OCRSTART;
CardStatus <= `STATUSSTART;	CardStatus <= `STATUSSTART;
CID<=`CIDSTART;	CID<=`CIDSTART;
	CSD<=`CSDSTART;
`response_CMD<=0;`	`response_CMD<=0;`
`outDelayCnt<=0;`	`outDelayCnt<=0;`
`crcDat_rst<=1;`	`crcDat_rst<=1;`
`crcDat_en<=0;`	`crcDat_en<=0;`
`crcDat_in<=0;`	`crcDat_in<=0;`

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[/] [sdcard_mass_storage_controller/] [trunk/] [bench/] [sdc_dma/] [verilog/] [sdModel.v] - Diff between revs 127 and 135