| Line 135... |
Line 135... |
|
|
wire sd_cmd_oe;
|
wire sd_cmd_oe;
|
wire sd_dat_oe;
|
wire sd_dat_oe;
|
wire cmdIn;
|
wire cmdIn;
|
wire [3:0] datIn;
|
wire [3:0] datIn;
|
|
wire card_detect;
|
trireg sd_cmd;
|
trireg sd_cmd;
|
tri [3:0] sd_dat;
|
tri [3:0] sd_dat;
|
|
|
assign sd_cmd = sd_cmd_oe ? cmdIn: 1'bz;
|
assign sd_cmd = sd_cmd_oe ? cmdIn: 1'bz;
|
assign sd_dat = sd_dat_oe ? datIn : 4'bz;
|
assign sd_dat = sd_dat_oe ? datIn : 4'bz;
|
|
assign card_detect = 1'b1;
|
reg succes;
|
reg succes;
|
sdModel sdModelTB0
|
sdModel sdModelTB0
|
(
|
(
|
.sdClk (sd_clk_pad_o),
|
.sdClk (sd_clk_pad_o),
|
.cmd (sd_cmd),
|
.cmd (sd_cmd),
|
| Line 181... |
Line 182... |
.sd_cmd_out_o (cmdIn ),
|
.sd_cmd_out_o (cmdIn ),
|
.sd_cmd_oe_o (sd_cmd_oe),
|
.sd_cmd_oe_o (sd_cmd_oe),
|
.sd_dat_dat_i ( sd_dat ), //sd_dat_pad_io),
|
.sd_dat_dat_i ( sd_dat ), //sd_dat_pad_io),
|
.sd_dat_out_o (datIn ) ,
|
.sd_dat_out_o (datIn ) ,
|
.sd_dat_oe_o ( sd_dat_oe ),
|
.sd_dat_oe_o ( sd_dat_oe ),
|
.sd_clk_o_pad (sd_clk_pad_o)
|
.sd_clk_o_pad (sd_clk_pad_o),
|
|
.card_detect (card_detect)
|
`ifdef SD_CLK_SEP
|
`ifdef SD_CLK_SEP
|
,sd_clk_i_pad
|
,sd_clk_i_pad
|
`endif
|
`endif
|
`ifdef IRQ_ENABLE
|
`ifdef IRQ_ENABLE
|
,.int_a (int_a),
|
,.int_a (int_a),
|
| Line 365... |
Line 367... |
$display("===========================================================================");
|
$display("===========================================================================");
|
$display("T5 test_send_cmd_error_rsp Complete");
|
$display("T5 test_send_cmd_error_rsp Complete");
|
$display("===========================================================================");
|
$display("===========================================================================");
|
|
|
// test_send_rec_data_error_rsp
|
// test_send_rec_data_error_rsp
|
//test_send_rec_data_error_rsp(0, 1);
|
test_send_rec_data_error_rsp(0, 1);
|
// $display("");
|
// $display("");
|
// $display("===========================================================================");
|
// $display("===========================================================================");
|
// $display("T6 test_send_cmd_error_rsp Complete");
|
$display("T6 test_send_cmd_error_rsp Complete");
|
// $display("===========================================================================");
|
// $display("===========================================================================");
|
$display("All Tests past");
|
$display("All Test finnished. Nr Failed: %d, Nr Succes: %d", tests_failed,tests_successfull);
|
succes = 1'b1;
|
succes = 1'b1;
|
end
|
end
|
|
|
|
|
|
|
| Line 573... |
Line 575... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0] != 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 709... |
Line 711... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0] != 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
`TIME;
|
`TIME;
|
| Line 731... |
Line 733... |
|
|
//wait for send finnish or timeout
|
//wait for send finnish or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0] != 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
tmp_data=1;
|
tmp_data=1;
|
end
|
end
|
| Line 752... |
Line 754... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0] != 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 775... |
Line 777... |
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0] != 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 803... |
Line 805... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 832... |
Line 834... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 862... |
Line 864... |
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 888... |
Line 890... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 911... |
Line 913... |
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1112... |
Line 1114... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0]!= 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
`TIME;
|
`TIME;
|
| Line 1134... |
Line 1136... |
|
|
//wait for send finnish or timeout
|
//wait for send finnish or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
tmp_data=1;
|
tmp_data=1;
|
end
|
end
|
| Line 1155... |
Line 1157... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1178... |
Line 1180... |
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1206... |
Line 1208... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1235... |
Line 1237... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1265... |
Line 1267... |
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1291... |
Line 1293... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1314... |
Line 1316... |
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1524... |
Line 1526... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0]!= 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
test_fail_num("Error occured when sending CMD0 in TEST4.0", i_addr);
|
`TIME;
|
`TIME;
|
| Line 1546... |
Line 1548... |
|
|
//wait for send finnish or timeout
|
//wait for send finnish or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
|
tmp_data=1;
|
tmp_data=1;
|
end
|
end
|
| Line 1567... |
Line 1569... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1590... |
Line 1592... |
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1618... |
Line 1620... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1647... |
Line 1649... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1677... |
Line 1679... |
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
data[31:16] = card_rca; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1703... |
Line 1705... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1726... |
Line 1728... |
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
data = 2; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1885... |
Line 1887... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0]!= 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
test_fail_num("Error occured when sending CMD0 in TEST0", i_addr);
|
test_fail_num("Error occured when sending CMD0 in TEST0", i_addr);
|
`TIME;
|
`TIME;
|
| Line 1907... |
Line 1909... |
|
|
//wait for send finnish or timeout
|
//wait for send finnish or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
data = 0; //CMD index 8, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
$display("V 1.0 Card, Timeout In TEST 3.0 %h", tmp_data);
|
$display("V 1.0 Card, Timeout In TEST 3.0 %h", tmp_data);
|
tmp_data=1;
|
tmp_data=1;
|
end
|
end
|
| Line 1928... |
Line 1930... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1951... |
Line 1953... |
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 1979... |
Line 1981... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2008... |
Line 2010... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2181... |
Line 2183... |
rsp = 16'hFFFF;
|
rsp = 16'hFFFF;
|
end
|
end
|
|
|
15: begin
|
15: begin
|
i_addr = `normal_isr;
|
i_addr = `normal_isr;
|
rsp = 16'h000;
|
rsp = 16'h0004;
|
end
|
end
|
|
|
|
|
|
|
|
|
| Line 2267... |
Line 2269... |
reg [3:0] rand_sel;
|
reg [3:0] rand_sel;
|
reg [31:0] data_max;
|
reg [31:0] data_max;
|
reg [31:0] rsp;
|
reg [31:0] rsp;
|
begin
|
begin
|
// test_send_cmd
|
// test_send_cmd
|
test_heading("Send CMD, with simulated bus error on SD_CMD line");
|
test_heading("Send CMD, With simulated bus error on SD_CMD line");
|
$display(" ");
|
$display(" ");
|
$display("test_send_cmd_error_rsp");
|
$display("test_send_cmd_error_rsp");
|
fail = 0;
|
fail = 0;
|
|
|
// reset MAC registers
|
// reset MAC registers
|
| Line 2335... |
Line 2337... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0]!= 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
|
|
if (tmp_data[15]) begin
|
if (tmp_data[15]) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
| Line 2394... |
Line 2396... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2457... |
Line 2459... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data == 0) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
|
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
`TIME;
|
`TIME;
|
$display("Bus error catched, Error status reg: %h", tmp_data);
|
$display("Bus error succesfully catched, Error status register: %h", tmp_data);
|
|
tmp_data[0]=1;
|
end
|
end
|
|
|
end
|
end
|
|
|
addr = `SD_BASE + `normal_isr ;
|
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
if (tmp_data[15]) begin
|
|
|
|
`TIME;
|
|
$display("Normal status register is 0x1: %h, bus error succesfully captured", tmp_data);
|
|
end
|
|
else begin
|
|
test_fail_num("Bus error wasent captured, Normal status register is: %h",tmp_data);
|
|
`TIME;
|
|
$display("Bus error wasent captured, Normal status register is : %h",tmp_data);
|
|
fail = fail + 1;
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
end
|
end
|
|
|
|
|
if (test_num == 3) //
|
if (test_num == 3) //
|
begin
|
begin
|
test_name = " Test 5 part 4: Send CMD2, 136-Bit ";
|
test_name = " Test 5 part 4: Send CMD2, 136-Bit ";
|
`TIME; $display(" Test 5 part 4: Send CMD2, 136-Bit ");
|
`TIME; $display(" Test 5 part 4: Send CMD2, 136-Bit ");
|
wbm_init_waits = 0;
|
wbm_init_waits = 0;
|
| Line 2528... |
Line 2520... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2664... |
Line 2656... |
|
|
//wait for send finnish
|
//wait for send finnish
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
data = 0; //CMD index 0, Erro check =0, rsp = 0;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1)
|
while (tmp_data[0]!= 1)
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//When send finnish check if any error
|
//When send finnish check if any error
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
data = 0;
|
data = 0;
|
| Line 2727... |
Line 2719... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2790... |
Line 2782... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
| Line 2853... |
Line 2845... |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
|
|
|
//wait for response or timeout
|
//wait for response or timeout
|
addr = `SD_BASE + `normal_isr ;
|
addr = `SD_BASE + `normal_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
while (tmp_data != 1) begin
|
while (tmp_data[0]!= 1) begin
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
if (tmp_data[15]== 1) begin
|
if (tmp_data[15]== 1) begin
|
fail = fail + 1;
|
fail = fail + 1;
|
addr = `SD_BASE + `error_isr ;
|
addr = `SD_BASE + `error_isr ;
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
|
